circuit diagram of digital clock using counters

Circuit Diagram Of Digital Clock Using Counters

Digital clocks of different kinds have been built by countless hobbyists over the world. A digital clock is shown named as circuit diagram of digital clock using counters!

It’s my st& that just looking at the circuit diagram & replicating it on a bread-board is not what electronics is about. Almost all digital circuits from traffic lights etc. to even computers are all based on sequential logic (its importance). Therefore, I have included the theory of flip-flops & sequential logic design in hope that it would help the reader to design circuits of their own. I have tried my best to describe sequential logic design between Step 3 to 8. However, if all you want is the clock then please skip everything from step 3-8. But if you go through those steps you ‘ll understand how to work with flip-flops etc. & though it takes a lot of time I can assure that you ‘ll be left with a wealth of knowledge.

circuit diagram of digital clock using counters
circuit diagram of digital clock using counters

Usual clocks that are based on decade counters have an hour counter from 0 -23. I have only used IC’s but still got a 12 hour clock, which I’ve not seen elsewhere. I’ve also added a small alarm module. The alarm is again achieved using IC’s not by programming boards (which quite honestly is comparatively easy). It is not much but I did whatever extra nicks I could do. The main emphasis however, is learning sequential logic & developing a breadboard based clock using that knowledge. For your kind attention: I ‘ll assume that you know basic high school level digital logic – the fundamental logic gates & binary numbers.

Step 1: The Logic of the Clock

circuit diagram of digital clock using counters
circuit diagram of digital clock using counters

As said earlier, our clock is a 12 hour clock. So, the clock we want is something like this HH : MM : SS A/P. Now, SS may also be referred as S1 S0 & the same goes for MM.

S0 counts from 0 to 9 & then S1 becomes 1 & S0 counts again. Our seconds count is from 0 – 59. So our S1 counter has to count only from 0-5. S0 counts 0-9. Thus 0 – 59 ‘ll be obtained. Now when seconds becomes 60, it is one minute. So everytime SS reaches 60, M0 (minutes) should increase by 1.

M1 & M0 essentially count the same way as seconds. So, a 1 second pulse provided to make it count from 0 – 9. Whenever S0 reaches 10, a pulse (digital parlance – clock signal) has to be generated to make S0 zero again (digital parlance – reset) & S1 one & the process repeats to make S1 two & so on. Thus S1 S0 ‘ll count from 0 – 59. Everytime SS reaches 60 a pulse needs to be generated to make M0 one & SS 00. For every 60 seconds, SS ‘ll go to 59 & back to 0, while MM is incremented. The MM counting is similar to SS but MM receives its clock (triggering pulse) from SS.

Remember MM is also 0 – 59. So, similar to how when, SS incremented MM when it turned 0 after 59 (it doesnt become 60), MM also should become 00 incrementing HH by 1. HH is a 1 – 12 counter. So when HH becomes 12, A (AM) is changed to P (PM) & vice-versa. So let’s say the time is initially 11:59:59 A. The next second it ‘ll become, 12:00:00 P. The day passes & now the time is 11:59:59 P. The next second it ‘ll become 12:00:00 A. This repeats for as long as the clock runs.

This is the logic of circuit. We have to design a 0-9 counter for S0 & M0, 0-5 counter for S1 & M1 & 1 – 12 counter for HH. A/P doesn’t need a counter, it just needs to alternate between these two states.

The alarm is done by means of a magnitude comparator. A 8 pin dip switch is used to enter 8 bits of data. Note HH (1 – 12) is 4 bits & M1 (0 – 5) is 3 bits. A/P is 1 bit. So if ABCDEFGH are the 8 pins from left to right, ABCD is entered for hours, EFG is for minutes & H is for A/P (M).

To set an alarm for 06: 30 AM, one needs to enter the binary value of 6 in ABCD (0110), 3 in EFG (011) & 1 (for A) in H. Note our alarm can be set only for 6: 30 or 6: 40 not any value in between. I think I can assume anybody who has enough technical knowledge to construct the clock ‘ll be able to enter the binary equivalent of decimals as shown above.

When the clock data equals to 8 pin dip switch data, the comparator’s A=B truth value becomes high, which is used to trigger an alarm with another flip-flop. The reset of the flip-flop ‘ll enable us to silent the alarm. I guess that is as far as the logic in the circuit goes to. From now it is design & implementation.

Step 2: Block Diagram

circuit diagram of digital clock using counters
circuit diagram of digital clock using counters

To avoid blocking up space, the alarm module is provided a separate block diagram. The working of the block diagram is described in detail here. Parts of this section, might seem like the repetition of he logic of the circuit discussed before, but bear it with me.

A 1 Hz (signal at every 1 second interval) square wave from an astable multivibrator is applied as a clock signal to the S0 counter which counts from 0 to 9 after every second. After 9, the values reset back to 0. Whenever S0 (4 bits) becomes 0000, a clock signal needs to be generated. This clock signal is applied to S1 counter which counts from 0 to 5. After it reaches 5 & S0 becomes 9, the next pulse ‘ll make both S1 & S0 zero.

When S1 (3 bits) becomes 000, a clock is generated & applied onto M0. This is extended to M1 just like S1. & similar to S1 when M1 (also 3 bits) becomes 000, a clock pulse is applied to HH. HH is a 4 bit counter counting from 1 – 12. Here every time HH becomes 12, a clock pulse if used to toggle A to P or P to A.

Each S0, S1, M0 & M1 counter’s data is converted to 7 segment display format & applied to a 7 segment display. HH requires a Binary to BCD (Binary Coded Decimals) converter. So, the 7 segment display shows the time as it is stored in the flip-flops.

The alarm module uses an 8 bit comparator to accept the user defined time. As described earlier, the first 4 bits are dedicated to HH, the next 3 bits are M1 & the last bit is to accept A/P. This 8 bit data is denoted A. The input from the dip switch is provided to the comparator. The corresponding bits of data are also applied from the flip-flops. The logic is that when the time as counted in the flip-flops is the same as that of the dip switch, the comparator’s A=B ‘ll become 1. This is used to toggle another flip-flop (its dedicated to this function alone) which is interfaced with the alarm. So, when A = B, the alarm sounds & it keeps sounding until the flip-flop is manually reset to 0.

Some of you might think, we can set alarm only for times like 4: 30, 4:40 & during these times the A = B ‘ll be ‘1’ for 10 minutes. For example, if we set te alarm for 4: 30 PM, then the comparator output A = B ‘ll be 1 for 4:30 PM to 4: 39 PM because only M1 values are compared & M1 values are same.

So A = B is 1 for 10 minutes. Is that a problem? It is not because most flip-fops currently employed are edge triggered. What is edge triggering? To understand that, we have to understand flip-flops.

Step 3: Basics of D & T Filp-Flops

circuit diagram of digital clock using counters
circuit diagram of digital clock using counters

In digital electronics, it was realized that you needed to remember past values to calculate new ones. For example, take our very own counters. You need to know what the previous number was, so that you can count to the next number. Only if you knew the previous number is 2 you can say the next number is 3 right?

By definition, a circuit whose present output depends on present input & past output is called a sequential circuit. Counters are sequential circuits. So, we had to find a way to remember the previous state. This led to the development of a latch. A latch is a simple circuit that “latches on” or stores 1 or 0.

Step 4: Designing Sequential Logic

circuit diagram of digital clock using counters

  [images cols=”three” lightbox=”true” description=”circuit diagram of digital clock using counters”]
[image link=”320″ image=”320″]
[image link=”321″ image=”321″]
[image link=”322″ image=”322″]
[/images]

Simple Boolean expressions like A+B or A . B’ are all called combinational logic. Combinational logic when combined with memory is called sequential logic. Because it allows combinations to be made in sequences or recurring patterns.

Sequential logic design is quite simple if combination logic design is known – Karnaugh or K- Map reduction (generally Quine-Mculskey method is not used since that level of complexity is hardly used by hobbyists).

So we ‘ll look into how K map simplification is done. For sake of explanation, let us consider 3 bits A, B, C. The output Q is high for few arbitrary values of A, B, C. Now from this, we have to form the Boolean expression (fancy term for digital expression) for C in terms of A,B, C. That’s the purpose of a Karnaugh map or simply K-Maps.

Fair warning: It is almost impossible to understand K- Maps at first, but the more & more you see it again & again it becomes very easy. When I saw it for the first time it was ghastly, now it’s a pass time like bingo!

Step 5: 0 – 9 counter using D- FF

 circuit diagram of digital clock using counters circuit diagram of digital clock using counters

NOTE: The next four steps (including this one) are to gain knowledge of working & designing logic with flip-flops. These steps are not required for the clock’s final implementation. But these steps ‘ll show you why we use IC 7493.

For the sequential logic refer to the scanned file. Our objective is to now construct the counter.

Components Required:

IC 7474: 2 Nos.

IC 7411: 1 No.

IC 7408: 1 No.

IC 7432: 1 No.

IC 7447: 1 No.

IC 555: 1 No.

Capacitors: 1000 uF & 0.01 uF (1 each)

Resistors: 470 ohms (1), 500 ohms (1) & 330 ohms (7)

Common Anode 7 segment Display: 1 No.

Breadboard & Power supply

Obviously we need 4 D flip – flops (for the 4 bits). The best choice is to use IC 7474. Each IC has 2 flip-flops. So we ‘ll need a total of 2 IC 7474 chips.

From the design we also may know that we need three – 3 input and gates. IC 7411 is a 3 input and gate & each IC has three and gates. So we ‘ll need 1 IC 7411.

We need four – 2 input and gates. For this we ‘ll use IC 7408. Each IC has four and gates, so we ‘ll need only 1 IC 7408.

We also need three 2 input OR gates. For this we ‘ll use IC 7432. Again this IC has four OR gates, we need only three but anyway we ‘ll use 1 IC 7432.

& yes, we want to see the output so a 7 segment display (I used common anode 7 segment display with IC 7447).

Construction:

There is not much of instructions I can provide for the connections. Just use a breadboard & connect the Vcc and ground to all the IC’s first. It is better to keep the IC 7447 & the display on a separate adjoining board.

I have uploaded the pin configurations of all the IC’s & the display that are used in the counter. Use that as reference & just follow the designed logic.

First connect the clock signal from a 555 Astable multivibrator (a clock with a slow enough frequency to observe changes, we ‘ll worry about accuracy later). This is really a common circuit so I am not gonna discuss that but use the uploaded schematic. Connect the clock to the 4 flip-flops (this is a synchronous circuit). Then start with D0 & do the combinational logic for D1, D2 & D3 one by one.

We are not using PRESET & CLEAR for this circuit, so you may either leave them open (without connections) or connect it to Vcc. I prefer the former option – just leave it.

In the 7447 pin configuration, you ‘ll find DCBA as the inputs. Q3 is D, Q2 is C, Q1 is B & Q0 is A. Connect a, b, c, d, e, f, g of the IC 7447 to the corresponding pins of the 7 segment display as in the pin diagram through a current limiting resistor of 330 ohms. Since we use a common anode display, connect the common terminal (COM in pin diagram) to Vcc.

Remember, the Q of the flip-flop you designate D0 is Q0. & in the same way, Q of D1 is Q1, Q of D2 is Q2 & Q of D3 is Q3. You interchange any, the circuit ‘ll not work. Strictly adhere to the pin configurations.

Step 6: 0 – 5 counter using D – FF

 circuit diagram of digital clock using counterscircuit diagram of digital clock using countersThis is quite similar to the 0-9 circuit except that the design changes & the circuit as such is comparatively smaller & requires less wires. Check the design in the scanned file.

Components:

IC 7474: 2 Nos.

IC 7411: 1 No.

IC 7408: 1 No.

IC 7432: 1 No.

IC 7447: 1 No.

IC 555: 1 No.

Capacitors: 1000 uF & 0.01 uF (1 each)

Resistors: 470 ohms (1), 500 ohms (1) & 330 ohms (7)

Common anode 7 segment display: 1 No.

Breadboard & Power supply

Here we need only 3 D flip-flops for the 3 bits, but we ‘ll have to use two IC 7474 anyway.

We also need 1 IC 7411 (for the one 3 input & operation), 1 IC 7408 (for the three 2 input & operations) & 1 IC 7432 (for the two 2 input OR operation). In practical terms gates & operations can be used interchangeably, as in 2 input and gate is almost same as saying 2 input & operation in practical terms.

The IC 7447 & the 7 segment display usage is the same as the previous case. In this case while connecting IC 7447, we use only 3 bits so only C for Q2, B for Q1 & A for Q0. Connect D terminal to the ground (do not leave it open).

Construction:

Pretty much the rest of the circuit is the same & off the 4 flip-flops in the 2 IC 7474’s, we ‘ll only use three of them so do not bother about the fourth 4th. Just leave that unconnected. & for the other terminals like PRESET & CLEAR – I suggest leave them too.

We need a clock again for the circuit & pretty much do the connections just like said before. First the Vcc and ground & then the clock to the flip-flops. Then the combinational logic for D0, D1 & D2.

As said before, Q of the flip-flop you designate D0 is Q0. & in the same way, Q of D1 is Q1 & Q of D2 is Q2. Do not mix it up!

Step 7: 0 – 9 Counter using T – FF

 circuit diagram of digital clock using counterscircuit diagram of digital clock using counters7a

I have done this circuit in an asynchronous way. The two counters we saw till now work in an synchronous way. Read through the first scanned file where I have explained the difference.

Hoping that you have read it, now you ‘ll remember that I said connect the 555 timer output to all the clock terminals of the flip-flops used in the 0-9 & 0-5 D flip counter. That is what makes them synchronous counters or in general synchronous circuits.

The same 0 – 9 & 0 – 5 counter can also be done in an asynchronous way which is what the next two counters ‘ll be about.

It is again an instance where it is not possible for me to explain the circuit by typing, so look into the second scanned file.

Components:

IC 7476: 2 Nos.

IC 7420: 1 No.

IC 7447: 1 No.

IC 555: 1 No.

Capacitors: 1000 uF & 0.01 uF (1 each)

Resistors: 470 ohms (1), 500 ohms (1) & 330 ohms (7)

Common Anode 7 segment Display: 1 No.

Breadboard & Power supply

As seen from the circuit diagram, we ‘ll need 4 T flip-flops. As such there is no commercial T flip-flop IC. So use a JK flip-flop – IC 7476 & short circuit or connect J & K terminals. That connected J & K terminals ‘ll be our T terminal.

We ‘ll need one 4 input Nand gate for which we ‘ll use a IC 7420. This Nand gate’s output is interfaced with the CLEAR of all the 4 T flip-flops.

Construction:

Again you ‘ll see terminals like 1K, 2K etc. Connect 1K to 1J & that ‘ll be 1T or the T terminal of the first flip-flop in the IC. 2J & 2K for 2T.

The display part of the circuit remains the same with Q3 being D, Q2 being C, Q1 being B & Q0 being A for the inputs of IC 7447. The 7 segment connections from IC 7447 also do not change.

Be careful while connecting the clock. We still need a 555 timer, but the timer’s output is interfaced with only the first flip-flop (or the flip-flop whose output is Q0). Then just follow the connections as in the second scanned file.

Step 8: 0 – 5 counter using T – FF

 circuit diagram of digital clock using counters circuit diagram of digital clock using counters

This circuit as well doesn’t change much from the 0-9 counter. For the circuit refer the scanned file.

Components:

IC 7476: 2 Nos.

IC 7410: 1 No.

IC 7447: 1 No.

IC 555: 1 No.

Common Anode 7 segment display: 1 No.

Capacitors: 1000 uF & 0.01 uF (1 each)

Resistors: 470 ohms (1), 500 ohms (1) & 330 ohms (7)

Breadboard & Power supply

As earlier, we need three bits or only 3 T flip-flops but anyways we ‘ve to use 2 IC 7476. & the J & K have to be connected & they are together the T terminal.

Since this circuit requires only 3 bits, we need only a 3 input Nand gate. So we use IC 7410.

Construction:

Connect ‘T’ to Vcc & connect Q to the next stage clock as shown in the schematic.

The outputs of the 3 input Nand gate is interfaced with the CLEAR terminals of the three connected flip-flops.

We use a 555 timer again connected only to the 1st flip-flop. Then it’s asynchronous connections.

Towards the display side, Q2 is C, Q1 is B & Q0 is A & D is grounded since we require only 3 bits. The rest of the display connections are the same.

It is important to note that doesn’t matter how many T flip-flops you connect in such an asynchronous way. The working does not vary.

So, it is very simple to use asynchronous circuits for counters because they use less connections & very little combinational logic. So, why are synchronous circuits important & why were excitation tables discussed? Well asynchronous are simple but they lack variety, it means you could use them only as up or down counters that count consecutive numbers. Up counters are ascending; Down counters are descending. All clocks use only up-counters otherwise time would run backwards!

The word consecutive here is very important. An asynchronous circuit, counts 6 then 7 & so on (up counter) or it counts 6 then 5 & so on (down counter). But what if I wanted to count only even number or odd numbers? There, you have no choice but to use synchronous circuits & excitation tables. Using synchronous circuits any r&om sequence can be done like from 1 to 5 then to 2 & then to 9 or whatever single loop sequence. So the choice between asynchronous or synchronous circuits depend simply on your purpose.

Step 9: Why 7493?

  circuit diagram of digital clock using counters9a

For non consecutive sequences, you ‘ve to go with synchronous circuits but for the purpose like clocks where the counting sequence is consecutive, it is quite better to go with asynchronous circuits because they are simpler to construct.

So, it’s decided that we ‘ll use asynchronous logic for our clock. But even asynchronous logic requires 3 or 4 IC’s for each counter. Since we recommend multiple counters, what do we do for not cramping space? We use IC 7493.

Take a look at the architecture IC 7493. If you connect Qa to input B, we get our 4 bit T flip-flop (all J & K are internally interfaced with Vcc) asynchronous counter.

For a 0 – 9 counter, 1010 (10) has to be used as the reset trigger. So Qd & Qb are interfaced with R0(1) & R0(2) respectively & we have our 0 – 9 counter.

R0(1) & R0(2) are internally interfaced with a Nand gate which is interfaced with the CLEAR of all 4 flip-flops. It has the 4 T flip-flops & the Nand gate built-in. Input A is provided the external clock connection from a 555 astable multivibrator. Qa is interfaced with Input B to complete the asynchronous connection.

If you use IC 7493, there are only few connections necessary. External clock input from a 555 timer etc. to Input A (Terminal 14). Qa (terminal 12) interfaced with Input B (terminal 1). Qd, Qc, Qb, Qa of IC 7493 are provided as inputs DCBA of the IC 7447 & the rest of the display connections are the same with the current limiting resistors. The required resetting connections (which differ for 0-5 counter & 0 -9 counter) have to be made.

For a 0 – 5 counter, we use 0110 (6) as the reset trigger. So again Qa is interfaced with input B to get our 4 bit asynchronous counter. Now Qb & Qc are interfaced with R0(1) & R0(2) respectively & we have our 0 – 5 counter. These circuits are pretty straight forward if you just refer the pin diagram.

It is for simplicity & restricted space that we use these 7493 counters for M1, M0, S1 & S0. Co0mmonly a problem may have different solutions. For example, the same 0 – 9 counter can be done in several manners but we chose the most appropriate & optimum solution which is the IC 7493 based counter.

Step 10: 1 – 12 counter using T – FF

 circuit diagram of digital clock using counters

circuit diagram of digital clock using counters circuit diagram of digital clock using counters

We also cannot use IC 7493 for such counter. We cannot use it for a1 to 12 counter because the Nand gate’s output is interfaced with all the CLEARS but not the PRESET. Actually, to the best of my knowledge, there is no IC counter that has PRESET functions other than this. So, we ‘ve to build this counter from only basic flip-flops.

We could have one simple 1-12 counter made from 4 flip-flops & use a Binary-BCD converter & use that for display. It must be kept in mind that the displays only display numbers from 0 to 9. That is why, by applying 10, 11 and 12 directly, binary values ‘ll provide an unwanted output. So we have to use a Binary to BCD converter or IC 74185.

As I was determined to get a 1 – 12 counter for my hours (perhaps that is why most of other clocks have 0 to 23 counters, it is easy), I have found a solution. This trick was to use 4 T flip-flops along-with 1 D Flip-Flop. The 4 T flip-flops are interfaced with the first display (the right h& side one) & the one D flip-flop is interfaced with the other (left h& side).

The 4 T flip-flops are interfaced with work as a 0 to 9 counter as seen in Step 7. The number 10 (1010) is used as a reset trigger, thus Q3 & Q1 are interfaced with a Nand gate whose output clears all the T flip-flops & PRESET the D flip-flop to 1. So, now the total output is 1 0. Then the T flip-flops count again from 0 to 1 & then 2 corresponding outputs would be 10, 11 & 12 in total. Now 3 (0011) is the required reset trigger but the Q of D flip-flop is also utilized. The Q of D flip-flop & Q1 & Q0 of the 4-bit T flip-flop counter is interfaced with a 3-input Nand gate. The output of that 3 input Nand gates is provided to the all flip-flops’ clears except Q0. The T flip-flop corresponding to Q0 is preset to 1. So we get 0 1 as the total output. Thus we get the 1 to 12 counter.

This is only theoretically, practically when I had obtained outputs from two Nand gates interfaced with Clears of the flip-flop in parallel. It such happens as the clearing function is over written & we get a free running counter. This happens because when one Nand output is 0 (let’s say it is 0 because the T flip-flop check out is browse 1010 & has to explicit), the other Nand so out-turn is 1 (when output is 9 recall the D flip-flop Q is 0,so that Nand output is 1). So, the 0 from the first Nand that should ‘ve cleared the check out back to 0 doesn’t clear whatever because of the 1 connected in similar trend. To prevail over  this the two Nand outputs are interfaced with an AND gate whose output is provided to clears & fixed. So, when one Nand gate is 1 & the other 0, the output is 0 which activate the amend but for most types both outputs ‘ll be 1 & & output is too 1. (The two Nand outputs can not ever both be 0 because 10 is not uniform to 13)

It’s actually hard to write in words, what took me 7 hours of correcting error after error for the final output. I hope you find the logic diagrams in the second scanned file useful.

Components:

IC 7447: 2 Nos.

IC 7410: 1 No.

IC 7476: 2 Nos.

IC 7408: 1 No.

IC 7474: 1 No.

Common Anode 7 segment display: 2 Nos.

IC 555: 1 No.

Resistors: 470 ohms (1), 500 ohms (1) & 330 ohms (13)

Capacitors: 1000 uF & 0.01 uF (1 each)

The components would be two 7476 IC from which the 4 T flip-flops are achieved. 1 D flip-flop 7474 (If you notice, the D flip-flop output is either 0 or 1 alternatively, so yes you can alternatively use another T flip-flop too). You ‘ll also need a 3 input Nand gate IC 7410 & an and gate IC 7408.

Construction:

First do the 4 bit T flip-flop counter as seen in Step 7.

See if it works then use a 3 input Nand gate with 1 input interfaced with Vcc & the other two being Q3 & Q1 of the T flip-flop counter.

Take that Nand output to the input of an and gate (terminal 1) & also the preset in the D flip-flop. Remember each & IC 7408 has 4 and gates.

Thus when T flip-flop counter goes to 1010, D flip-flop ‘ll toggle to 1 while the 4 T flip-flops clear to 0.

The Q of the D flip-flop is interfaced with the input of another Nand gate. Q1 & Q0 are also interfaced with the same Nand gate. Its output is provided to the and gate (terminal 2) & also the CLEAR of the D flip-flop.

The output of the and gate (terminal 3) is interfaced with the CLEAR of Q3 & Q1.

Leave the Clear & Preset of Q2 & Q0 untouched, you ‘ll still get the required output.

This ‘ll explain why. The first clearing occurs when the T flip-flop count is 1010 (10), so if Q3 & Q1 are cleared we get, 0000 which is what we want. The second clearing comes into play when the T flip-flop counter is 0011 (of cousre D’s Q is 1 also but that is not relevant), so again if we clear just Q3 & Q1, the output is 0001, which is again what we long for! So, you can leave Q2 & Q0 untouched.

Many a times when we design a circuit, we might not get the components required or they might be too costly like the IC 74185. In such cases, you can always create an creative design which works with what is available but still provides the results you want. This counter is an example of that.

Step 11: A / P – Ante / Post Meridiem

 circuit diagram of digital clock using counters

This is not exactly a counter, but it’s the easiest of all the modules.

Components:

IC 7474: 1 No.

IC 555: 1 No.

Common Anode 7 segment display: 1 No.

Capacitors: 1000 uF & 0.01 uF (1 each)

Resistors: 470 ohms (1), 500 ohms (1) & 330 ohms (6)

Breadboard & Power supply

Construction:

For the A / P display corresponding to the AM / PM, the segment display is directly connected without any IC 7447. If you look at the pin configuration of the 7 segment display, you ‘ll notice that whether it is A or P segments a, b, f, g & e are always ON. So it is directly interfaced with the ground with a current limiting resistor of 330 ohms.

The difference between A & P, is in whether the segment ‘c’ glows or not. If ‘c’ segment glows, it displays A or else it’s just P. Segment ‘d’ is not used in both cases, so it is left without connections.

The segment ‘c’ is controlled by the output Q of a T flip-flop. If Q is high or ‘1’, it makes the segment ‘c’ glow which displays A. If Q is low or ‘0’, it makes the segment ‘c’ dull which displays P.

Even the c segment connection from the flip-flop is also through a current limiting resistor. A current limiting resistor of either 220 ohms or 330 ohms is essential or you ‘ll burn out your 7 segment display.

The required flip-flop is an IC 7474, with D interfaced with Q’ to be operated in toggle mode (alternates between 1 & 0 for every clock pulse, again a T flip-flop may also be used). The clock signal is obtained from a 555 timer for this implementation. So Q toggles between 1 & 0 back & forth, correspondingly displaying A & P. Thus the A / P display is obtained.

Since it’s a common anode display (Led glows when grounded or terminal voltage is low) practically it’s the reverse – Q = 1 displays P & 0 displays A. To overcome this confusion in the final implementation I have connected Q’ to the display terminal. For fact, in our circuit P is 0 & A is 1.

Step 12: Breadboard Implementation

circuit diagram of digital clock using counters

[images cols=”three” lightbox=”true”]
[image link=”338″ image=”338″]
[image link=”345″ image=”345″]
[image link=”344″ image=”344″]
[image link=”343″ image=”343″]
[image link=”342″ image=”342″]
[image link=”341″ image=”341″]
[image link=”340″ image=”340″]
[image link=”339″ image=”339″]
[image link=”346″ image=”346″]
[/images]

The most important thing to know is, when dealing with digital circuits Vcc almost always means 5V. I have not uploaded any schematic here. Refer the steps for each stage.

Components:

IC 7493: 4 Nos.

IC 7400: 1 No.

IC 7408: 1 No.

IC 7410: 1 No.

IC 7474: 2 Nos.

IC 7476: 2 Nos.

IC 74682: 1 No.

IC 7447: 6 Nos.

IC 555: 1 No.

Common Anode 7 segment display: 7 Nos.

Capacitor: 1000 uF, 0.01 uF (1 each)

Resistor: 470 ohms (1), 500 ohms (1), 330 ohms (48)

8 pin DIP switch: 1 No.

Buzzer: 1 No.

Breadboards & Power supply

Construction:

The best way to implement the circuit is to first start from one end (right to left) & do one circuit at a time. First complete the 0 – 9 counter using 7493 with a 1 Hz square wave as clock from a 555 timer as in step 9.

Once that counter works, connect the reset terminals of 7493 (terminals 2 & 3) to the two inputs of a Nand gate (7400 ‘ll do). The output of that Nand gate is the clock for the next stage.

Then do a 0 – 5 counter using 7493. Everything remains the same, the display etc. The reset terminals are provided Qc & Qa connections.

Again these two reset terminals are interfaced with a Nand gate whose output is the next stage clock.

Repeat this for another 0 – 9 counter & then a 0 – 5 counter.

Then construct the 1 – 12 counter, use another 555 timer done on a separate breadboard as clock for testing this 1 – 12 counter.

Once you have checked that it works then the Nand gate output, to which the last (minutes – M1) 0 – 5 counter’s resets are connected, is provided as clock signal to the 1 – 12 counter.

Then use an and gate to which the D flip-flop’s Q & the T flip-flop’s Q1 of the 1 – 12 counter are connected as inputs. Connect this and gate’s output to the clock of another D flip-flop operated in toggle mode (Q’ is interfaced with D).

This D flip-flop Q’ is interfaced with the ‘c’ terminal of the segment common anode display (all the other 6 common anode displays are interfaced with IC 7447, this one is not as in step 11). Terminals ‘a’, ‘b’, ‘e’, ‘f’ & ‘g’ are interfaced with ground while the common is provided to Vcc. Do not forget the current limiting resistor of 330 ohms for each a, b, c, e, f, g terminals used in the display.

Alarm module:

Then place the Dip switch, short-circuit all 8 connections on the OFF side (lower array of the DIP) & connect that to Vcc.

Connect 8 individual wires to the ON side array & connect it numbered from 1 to 8 to Q terminals of IC 74682 (8 bit magnitude comparator) from Q0 to Q7 (Refer the pin diagram uploaded).

Here’s where we have to do a little sacrifice, we may only use the 4 bits of the T – flip-flops in the 1 – 12 counter. 3 more bits from the 0 – 5 counter of the minutes & 1 bit for A/P.

So Q3, Q2, Q1 & Q0 of the T flip- flops are interfaced with P0, P1, P2, P3 respectively. Qc, Qb, Qa of the 0 – 5 counter in minutes is interfaced with P4, P5, P6 respectively. The A/P D flip-flop’s Q is interfaced with P7.

The P=Q terminal of the IC is interfaced with the clock of another D flip- flop which is also in toggle mode (D is interfaced with Q’).

Q’ is interfaced with the CLEAR of the flip-flop through a TACT switch which acts as the snooze button. The Q of the flip-flop is interfaced with a buzzer.

If you are using power supplies with a 5 V output most probably it won’t be enough to energise such a huge circuit. So you’ll have to connect another 5V power source in parallel. I have used the 12 – 0 output of my supply with a 7805 & connected them in parallel to increase the current supplied at 5V (connection in series increases voltage & IC’s ‘ll get screwed!).

The alarm works as follows. Assume D flip-flop’s Q is 0 initially. When the input value matches that of the corresponding clock value, the P=Q value changes from low to high. This positive edge triggers the D flip-flop to toggle. Thus Q becomes 1 & Q’ becomes 0. The buzzer interfaced with Q starts sounding & the alarm works.

circuit diagram of digital clock using counters
circuit diagram of digital clock using counters

Now there is a snooze button or the TACT switch connecting Q’ to CLEAR. Since Q’ is 0, when the TACT switch is pressed, CLEAR input becomes 0 & thus the D flip-flop clears making Q = 0. When Q becomes low, the buzzer doesn’t sound & the alarm is silenced. Thus we get our basic alarm.

Read Also>>  Circuit Diagram Of Calculator Using Logic Gates

 

Leave a Reply

Your email address will not be published. Required fields are marked *