D.c.-d.c. converter

D.c.-d.c. converter: The converter raises a direct volt-/ age to almost twice its level and is, therefore, particularly suited to increase the output of solar cells to the level required for charging lead-acid or NiCd batteries. It can deliver a current of up to 3 A. Measurements with a load current of 2 A is given in the table. The open-circuit output voltage is about 1-1.5 V higher.

In the following description, it is assumed that the input voltage to the circuit is 12 V and the output voltage 22 V. ICia, R2 and C5 form a rectangular-voltage generator. This signal is also available in inverted form at the output of ICid. Network R2C6 delay the output of IC1a, so that the output of NAND gate ICib has a duty factor >0.5 (the negative half is shorter than the positive half). The same is true of the output of NAND gate ICic. (The input signal to this gate is delayed by R5-C7).

The output of IC1c is inverted and buffered three times: in IC3f, 1C3a, and the four paralleled gates IC3b,-1C3e• It is then used to drive power FET T3.

The output of ICib drives small-signal transistor T1. When this transistor is on, junction R6-R7 is pulled to 2 V without diode D1. However, IC2a needs an input signal of 11-22 V, since the supply voltage for this inverter (and, of course, also for inverters 1C2b-IC2,), as well as the collector voltage of T1, is already derived from the doubled output voltage. The negative supply voltage for /this IC is therefore derived from the positive input voltage. Diode DI ensures that potential at the input of IC2a does not drop below 10.5 V.

Transistors T2 and T3 conduct alternately. When T2 is on, C10 is charged to the level of the input signal via T3 and D3. When T2 is off and T3 is on, C9 is charged similarly. Capacitor Coo retains its charge since D3 prevents it’s being discharged. Since the two capacitors are in series, the output voltage is twice the input potential.

Owing to the multiple inversion of both signals following the delay networks, it is impossible for T2 and T3 to be switched on simultaneously.

Capacitor C1 buffers the input signal so that its loading is constant in spite of the varying current drawn by the circuit.

It is essential that D2, D3, T2, and T3 are well cooled. It is best to mount these components on a common heat sink.

The bold lines in the circuit diagram represent heavy-duty wires that should be as short as possible since they carry a current of 6 A.

A carefully constructed converter should give an efficiency of 94% (at 22.2 V and 1.8 A).

Input and output voltages with a load current of 2 A are:

Uin

10  V

12  V

14  V

15  V

16 V

Uout

18  V

22  V

26.4  V

28.3  V

30  V

D.c.-d.c. converter Schematic diagram

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