During experiments with I2C circuits, it sometimes happens that the bus fails for no apparent reason. Since not everybody has a logic analyzer available. the circuit presented here may in a number of cases prove to be useful. It is no – more, and no less than a manually operated 12C output. The clock and data lines are made high or low with the aid of two switches. 1\vo LEDs indicate the levels as they are really on the bus. Note that if the 12C circuit has a built-in time-out (normally of about I ms), the present circuit is of no use, since it is impossible to react fast enough manually. The circuit on a test will ‘see’ a circuit that does not react and will cease its 12C routines. The present circuit consists of two identical halves: one for the data line (SDA) and the other for the clock (SCL). A change-over switch, S1 or S2, and a bistable, ICia or ICib, produce a logic 1 or 0. The bistable is essential to suppress the switch bounce, which, without fail, would be interpreted as a series of pulses. The position of the switch indicates whether a
1 or a 0 is applied to the bus. The real level on the bus is indicated by D1 and D2. This does not necessarily coincide with the level, that is applied by the present circuit because the bus has an open collector structure. It is for that reason that the outputs of the bistables are not connected directly to the bus but via T2 and T. respectively.
Pull-up resistors R4 and R11 are needed only once on the bus. so that they may be omitted if they are already present elsewhere.
The present circuit may also be used as a simple IBC monitor. With both switches in the ‘1’ position, the bus is not affected and the LEDs then show whether the bus is active. Much activity is needed. because a single transmission cannot be indicated by an LED.