PLL synthesizer for TV receivers

Modern TV tuners normally contain means to scale down the VCO (voltage-controlled oscillator) signal. The one used in the proposed synthesizer is a Philips Type UV816/6456, whose scale factor can be set to 64 or 256. It operates over the low VHF band, the high VHF and hyperbands, and the UHF band. The proposed circuit is based on a Siemens Type SDA3002 frequency synthesizer IC that may be controlled by a computer. It works exclusively with a: 64 scaler. This is ensured by leaving pin 15 of the tuner ‘open. Network R2-C2-C1 forms the filter for the phase-locked loop—PLL. The level of the charging current for the filter is determined by the value of R1 and bit 14— see Table 1. In the prototype, both low and high levels s of current gave stable PLL operation, but the loop reacted faster with
a high current.
The SDA3002 has a unique oscillator for providing a reference frequency. The frequency of crystal X1 is scaled down internally by 4096 so that the reference
a frequency for the PLL is 976.5625 Hz.

The PLL is set by entering a data word into the SDA3002, for which a clock, CPL, an enable signal, PLE, and a data signal, IFO, are needed. At each trailing transition (edge) of the clock, a bit is shifted into the IC, provided PLE is high—see Fig. 2. Only when PLE has become low will the PLLaccept the entered data into a latch.

A total of 18 bits must be shifted into the chip. Fourteen of these contain the frequency setting of the PLL. The 15th bit determines the charging current. When this bit is high, the current is 10Ir, where Ir is the reference current; when it is low, the

charging current is lr. The 16th bit controls the NORM output. The final two bits determine the state of the band selector outputs: pins 4-7, see Table 1.

The first 14 bits are computed fairly easily once the desired channel frequency, fc, the intermediate frequency. i.ƒ.(=38.9 MHz), the scale factor, za (=64) of the tuner, and the reference frequency, of the PLL are known. The overall scale factor, z, is then

z= (ƒc+i.ƒ.)/zaƒr.

The result should be rounded to the nearest whole number, and then split into two parts (IC1 contains a dual-mode prescaler) to obtain the bits needed by IC1. The nine most significant bits—MSBs—are calculated by dividing z by 32 and ignoring

the digits following the decimal point. The remainder of z:32 forms the five least significant bits—LSBs. As an example, assume that channel 29 is wanted; the carrier frequency is then 535.250 MHz. The scale factor is

z= (535.25+38.9)/64976.5625=
=9186.
Dividing that number by 32 gives 287, remainder 2. In binary form, that is (MSB)100011111 00010 (LSB). However, the data must be entered in an inverted form, that is, a logic I corresponds to low and a logic 0 to high. Taking the LSBs first, the following levels must appear at the data input

PLL synthesizer for TV receivers Schematic diagram

HLHHHLLLLLHHHL
Diode D1, which is controlled by the LOCK output via T1, then lights to indicate that PLL is locked.

The maximum tuning voltage is determined by the supply voltage. Which is connected to loop filter via R3. The UV816 needs a tuning voltage of 0.7-2.8V. The SDA3002 can handle the maximum voltage of 33V at its UD output.

Two further supplies are needed: 12V for the tuner and 5V for IC1 and prescaler in the tuner. Since the combined current drain of IC1 and D1 (lighted) is only 29mA, the 5V rail is easily obtained from the 12V supply via a 5V regulator. That regulator can at the same time provide the current –about 25mA–for the prescaler in the tuner. Additionally, the 12V supply must provide the current for a tuner, which in the case of UV816 is about 85mA. A total current of some 140mA is, therefore, required.

PLL synthesizer for TV receivers Schematic diagram

PLL synthesizer for TV receivers Schematic diagram

PLL synthesizer for TV receivers Schematic diagram

Leave a Reply

Your email address will not be published. Required fields are marked *