Robotics Circuit Diagrams

80C552 microprocessor system

Here is something for microcontroller enthusiasts to grind their teeth on. The 800552 microcontroller from Philips Components is an up-. ; railed derivative of Intel’s 8032. It costs lit-de more than the 8032, yet offers the following extras: (1) eight analogue inputs: (2) a 10-bit A-D converter: (3) a ‘Timer2: with many extra features: (4) a Timer3’ watchdog function; (5) an onboard 12C interface: (6) 161/O lines: (7) two pulse width modulation outputs; and (8) a 16-MHz clock.

Here, the 800552 is used in a single-board microcontroller application, which is intended as an experimental system rather than an a_ replacement for an existing processor. The board is aimed at the versatility and accepts EEPROMs, EPROMs, or RAMs, or a combination of these, as memory devices, The 800552 board offers a multitude of I/O connections for your own applications. All i/o lines, except PO and P2, are accessible via connectors K1, K2, K4, and K5. The 12C lines, P1 6 and P1.7, are taken to a simple 12C interface around a 6-way mini-DIN connector. K6. The TxD and RxD lines are available for TTL-level serial communication via two pins on connector K5, which also carries read, write, interrupt and timer signals. Those of you familiar with the 8032 processors will find that the address decoding circuit used here is fairly extensive.

80C552 microprocessor system Schematic diagram

Also, unusually, the reset input of the CPU is connected to a bistable. As to the address decoding, this must meet a number of special requirements: it must be possible to read instructions (using PSEN\) as well as read data (using RD) and write data (using WR). Further, it is possible to swap the address ranges of the IC4 and IC5 positions, with the CS1  (chip enable) inputs of the respective EPROMs (or EEPROMs) used to select and de-select them, so that the de-selected EPROM hardly consumes power. When the processor is switched to ‘idle’ mode, its current consumption is only one-third of the normal value, while the CS1  inputs of both EPROMs are automatically taken high, thus reducing power consumption even further.
Bistable ICIa and. XOR gate IC2b serve to swap the positions, 0000H- iFFFH and 2000H-3FFFH, of the two EPROMs in the address map. Provided EEPROMs are used, this allows an interesting program-ming trick: reload the .’upper’ EEPROM (i.e., the one with the highest address) with the aid of a program run from the ‘lower’ EEPROM. Look, no hands! No opening of
cases, no extracting of EPROMs, and no more time wasted on erasing and reprogramming EPROMs. For instance, the pr-gram in the ‘lower’ EEPROM may read the data supplied Ly. T2C or the serial input, organize it, store it into the upper’ EEPROM. Next, the program causes the To line to be pulled low and also stops triggering the watchdog. After some time, the watchdog will force an internal reset, • for which- also pulls RST (pin 15) high three, lee clock cycles. This works as a lock for bistable ICia. The bistable copies the level on TO to its Q output. This enables IC to .0 swap the EEPROM address that, oY inverting address line A13, so upper,”E, program just loaded into the r-VROM is executed.

Because interrupt vectors are always located from address 0000H, address ranges have to be swapped physically rather than in software. However, this swapping is not allowed while the CPU is about its normal business of fetching and executing codes because an address might change in the middle of an opcode fetch action. At a clock of 6 MHz, this can be done with impunity, but definitely not at a clock of 12 MHz or 16 MHz as used here, which forces us to use the ‘hardware reset’ trick. It should be noted that the analogue port, P5, may function as an input only (it may also be used to accept digital levels). The two 12C pins, SCL and SDA (P1.6 and P1.7), may be used as an input or an output. Contrary to the other I/O pins, they do not have internal pull-up resistors. Further, it is recommended not to use P3.7 and P3.6, as this will interfere with the normal opcode fetch operations. If you intend to connect an LCD(liquid crystal display) module to the 800552 system, it is best to use the LCD in 4-bit mode, because that allows the display to be connected to 7 port lines only. A direct bus connection is not possible at clock speeds higher than 10 MHz.

Parts list
Ri; R2: R3; R6; R8 = 10 kΩ
R4; R5 = 330 Ω
R7 = 8-way 10 kΩ SIL
C1; C5 = 22 nF
C2; C3; C4; C6 = 100 nF
C7 = 10 uF, 16 V radial
C8 = 4.7 pF, 16 V radial
D1 = 1N4148
D2; D3; D4 = 5.6 V, 0.4 W zener diOth
D5 = 1N4001
Integrated circuits
IC1 = 74HCT74
IC2 = 74HC786
IC3 = 74HCF00
IC4: IC5 = 27C64 (EPROM) or 28(C)64 (RAM) or 64(C)64 (EEPROM
IC6 = 74HCT573
IC7 = PCB80C552-4WP (16-MHz 68-PLCC)
IC8 = 7805
K1; K2; K4: K5 = 10-way box header.
K3 = 14-way box header.
K6 = 6-way Pcs-mount mini DIN socket.
X1 = 16MHz quartz crystal.
68-way PLCC socket.
PCB Ref. 924071.

80C552 microprocessor system Schematic diagram

80C552 microprocessor system Schematic diagram

80C552 microprocessor system Schematic diagram


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