Robotics Circuit Diagrams

80C552 Microprocessor System Schematic Circuit Diagram

80C552 microprocessor system: Here is something for microcontroller enthusiasts to grind their teeth on. The 800552 microcontroller from Philips Components is an upgraded derivative of Intel’s 8032. It costs a little more than the 8032, yet offers the following extras:

  1. Eight analog inputs:
  2. a 10-bit A-D converter:
  3. a ‘Timer2: with many extra features:
  4. a Timer3′ watchdog function;
  5. an onboard 12C interface:
  6. 161/O lines:
  7. two pulse width modulation outputs; and
  8. a 16-MHz clock.

Using the 800552 in a Single-Board Microcontroller Application

In this context, the 800552 is employed within a single-board microcontroller application designed for experimentation rather than serving as a replacement for an existing processor. The board prioritizes versatility and accommodates various memory devices, including EEPROMs, EPROMs, or RAMs, either individually or in combination. For user-specific applications, the 800552 board provides numerous I/O connections. All I/O lines, with the exception of PO and P2, can be accessed through connectors K1, K2, K4, and K5. The 12C lines, P1.6 and P1.7, are directed to a straightforward 12C interface utilizing a 6-way mini-DIN connector, K6. TTL-level serial communication via TxD and RxD lines is facilitated through two pins on connector K5, which also carries read, write, interrupt, and timer signals. Those acquainted with the 8032 processors will recognize that the employed address decoding circuit in this configuration is quite comprehensive.

80C552 microprocessor system Schematic diagram

Unconventional CPU Reset and Address Decoding Configuration

In an unconventional setup, the CPU’s reset input is intricately linked to a bistable component. Address decoding, in this case, is subject to several specific requirements. It must facilitate the reading of instructions (via PSEN), as well as the reading and writing of data (utilizing RD and WR). Moreover, a unique feature allows the interchangeability of address ranges between the IC4 and IC5 positions. The CS1 (chip enable) inputs of the respective EPROMs (or EEPROMs) are employed for selection and de-selection, ensuring that the de-selected EPROM consumes minimal power. When the processor transitions to ‘idle’ mode, its current consumption drops to one-third of the normal value. Simultaneously, the CS1 inputs of both EPROMs automatically go high, further minimizing power consumption.

Bistable and XOR Gate for EPROM Position Swapping

To dynamically switch the positions (0000H-1FFFH and 2000H-3FFFH) of the two EPROMs within the address map, a bistable IC1a and XOR gate IC2b are employed. This configuration, particularly useful when using EEPROMs, unlocks an intriguing programming technique. It enables the reloading of the ‘upper’ EEPROM (the one with the highest address) with a program executed from the ‘lower’ EEPROM without any physical intervention. This innovative approach eliminates the need to open cases, extract EPROMs, and saves time otherwise spent on erasing and reprogramming.

For instance, the program in the ‘lower’ EEPROM can read data from sources like T2C or serial input, organize it, and store it into the ‘upper’ EEPROM seamlessly. Subsequently, the program triggers the To line low, halting the watchdog, which, after some time, initiates an internal reset. This reset action pulls RST (pin 15) high for three clock cycles, effectively acting as a lock for bistable IC1a. The bistable mirrors the level on TO to its Q output, empowering IC2b to swap the EEPROM address, allowing the execution of the recently loaded program in the ‘upper’ EEPROM.

Physical Swapping of Address Ranges and Clock Considerations

Address ranges must be physically swapped instead of relying on software alterations because interrupt vectors are consistently located from address 0000H. Software-based swapping is deemed impractical as it might disrupt the CPU’s normal execution of fetching and executing codes. This is particularly crucial during opcode fetch actions, where a mid-opcode address change can occur. Although at a clock speed of 6 MHz, such swapping is unproblematic, it is not suitable for the 12 MHz or 16 MHz clock speeds utilized here. Therefore, the ‘hardware reset’ trick becomes necessary to avoid potential issues.

It’s worth noting that the analogue port, P5, functions exclusively as an input (capable of accepting digital levels as well). The two 12C pins, SCL and SDA (P1.6 and P1.7), can serve as either input or output, lacking internal pull-up resistors unlike other I/O pins. Additionally, it is advised against using P3.7 and P3.6 to prevent interference with normal opcode fetch operations. If connecting an LCD module to the 800552 system, opting for 4-bit mode is optimal, allowing the display to be linked to only 7 port lines. A direct bus connection becomes unfeasible at clock speeds exceeding 10 MHz.

Parts list

  • Ri; R2; R3; R6; R8 = 10 kΩ
  • R4; R5 = 330 Ω
  • R7 = 8-way 10 kΩ SIL
  • C1; C5 = 22 nF
  • C2; C3; C4; C6 = 100 nF
  • C7 = 10 uF, 16 V radial
  • C8 = 4.7 pF, 16 V radial
  • D1 = 1N4148
  • D2; D3; D4 = 5.6 V, 0.4 W zener diOth
  • D5 = 1N4001
Integrated circuits
  • IC1 = 74HCT74
  • IC2 = 74HC786
  • IC3 = 74HCF00
  • IC4: IC5 = 27C64 (EPROM) or 28C64 (RAM) or 64C64 (EEPROM)
  • IC6 = 74HCT573
  • IC7 = PCB80C552-4WP (16-MHz 68-PLCC)
  • IC8 = 7805
  • K1; K2; K4; K5 = 10-way box header.
  • K3 = 14-way box header.
  • K6 = 6-way PC-mount mini DIN socket.
  • X1 = 16 MHz quartz crystal
  • 68-way PLCC socket.
  • PCB Ref. 924071.

80C552 microprocessor system Schematic diagram

80C552 microprocessor system Schematic diagram

80C552 microprocessor system Schematic diagram


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