Customizable Audio Input Selection Circuit
This specialized circuit, tailored for audio applications, empowers users to choose the input signal to be activated upon system startup. The unique feature here is its flexibility; the selected input isn’t fixed but stored in an EEPROM, which the circuit reads during power application. Fortunately, with the decreasing cost of EEPROMs, this setup is now a cost-effective solution. The key component is a shaft encoder incorporating rotation outputs and a pushbutton (Conrad Electronics catalog number 70 55 94).
The rotation direction determination circuit, previously featured in Elektor Electronics, is integrated into this setup. Additionally, a debounce circuit is included for the pushbutton. At the core of the circuit lies a presettable decimal or binary up/down counter (IC3, either a 74HC193 or a 74HC192) equipped with separate clock inputs. The clock pulses from the shaft encoder undergo inversion via IC1.A and IC1.C. These signals then pass to NAND gates IC1.B and IC1.D, with their other inputs serving as control inputs, enabling selective passage of the clock pulses.
Controlled Counting and Directionality
In this setup, assuming the control input is high, the clock signal is directed to the counter IC3. With every negative edge, the counter either increments or decrements by one. The counter’s outputs are linked to the BCD-to-decimal decoder IC6. The ‘0’ and ‘8’ outputs from this decoder influence the control inputs of the NAND gates on the ‘down’ and ‘up’ clock inputs. This arrangement blocks negative edges from the shaft encoder when the counter is in the corresponding state, allowing counting only in the opposite direction.
Data Storage and Retrieval Mechanism
Upon pressing the pushbutton on the shaft encoder, the output of the counter at that moment is stored in the non-volatile EEPROM. The pushbutton signal, transformed by IC2.A into an inverted form, acts as an enable input for bus driver IC5. When the pushbutton is depressed, pin 19 goes low, driving the 4-bit value from counter IC3 onto the preset inputs of the counter and the I/O pins of EEPROM IC4. Concurrently, the EEPROM enters write mode (WE input low, OE input high), saving the data at location 0.
Upon release, the bus driver’s outputs return to a high impedance state, and the EEPROM shifts back to read mode. The stored counter value is then presented to the counter’s preset inputs. During power-up, C6 gradually charges, producing a low pulse on the load input of IC3. In this moment, as the EEPROM is in read mode, the data from address 0 moves to the counter’s preset inputs, transferred to the outputs by the load input’s low pulse.
