Audio Circuit DiagramsClock & Timer Circuit Diagrams

Audio input Selector Schematic Circuit Diagram

This circuit, designed for audio applications, allows the user to select which input signal will be enabled when the system is switched on. The setting is not fixed but is stored in an EEPROM which is read when power is applied. Fortunately, because of the falling price of EEPROMs, this is not an expensive proposition. The switch used here is a shaft encoder with rotation outputs and a pushbutton (Conrad Electronics catalog number 70 55 94). The circuit to determine the direction of rotation has appeared before in Elektor Electronics. A debounce circuit has been added for the pushbutton. The heart of the circuit is a presettable decimal or binary up/down counter (IC3, either a 74HC193 or a 74HC192) with separate clock inputs. The clock pulses from the shaft encoder are first inverted by IC1. A and IC1.C. The signals are then passed to NAND gates IC1.B and IC1.D: the other inputs of these gates are used as control inputs to enable the clock pulses to be passed through or not.

Audio input Selector Schematic Circuit Diagram

Assuming the control input is high, the clock signal is passed on to counter IC3. Each negative edge causes the counter to count up or down by one. The outputs of the counter are connected to BCD-to-decimal decoder IC6. The ‘0’ and ‘8’ outputs of this decoder are connected to the control inputs of the NAND gates on the ‘down’ and ‘up’ clock inputs respectively. This means that negative edges from the shaft encoder will be blocked when the counter is in the appropriate state, and the counter can therefore only count in the opposite direction.

When the pushbutton on the shaft encoder has pressed the output of the counter at that moment is stored in the non-volatile EEPROM. The pushbutton signal is connected to the enable input of bus driver IC5 via IC2.A, a NAND gate connected as an inverter. If the button is not being pressed, the enable input is high, so all outputs are high impedance, and IC5 is effectively not present. However, when pin 19 goes low the 4-bit value on the output of counter IC3 is driven on to the preset inputs of the counter and on to the I/O pins of EEPROM IC4. At the same time, the EEPROM is put into write mode by taking its WE input low and its OE input high. The data are then stored at location 0 (since the address pins A0 to A10 are held low). As soon as the pushbutton is released, the data outputs of the bus driver return to the high impedance state. The EEPROM switches back into a reading mode (with WE high and OE low), and presents the stored counter value to the preset inputs of the counter. As long as the load input of the counter IC3 remains high, the output of the counter is not affected. When the load input goes low, the values at the preset inputs are transferred to the count outputs A to D. This is exactly what happens when power is applied to the circuit: C6 charges slowly, applying an active-low pulse to the load input of IC3. Since the EEPROM is in reading mode at power-up, the data stored at address 0 will be available at the preset inputs to the counter and be transferred to the outputs by the low pulse on the load input.


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