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Baud Rate Generator Schematic Circuit Diagram

Elsewhere in this issue, an RC oscillator is used as a baud rate generator. If you can calibrate the frequency of such a circuit sufficiently accurately (within a few percent) using a frequency meter, it will work very well. However, it may well drift a bit after some time, and then…. Consequently, here we present a small crystal-controlled oscillator.

Baud Rate Generator Schematic Circuit Diagram

If you start with a crystal frequency of 2.45765 MHz and divide it by multiples of 2, you can very nicely obtain the well-known baud rates of 9600, 4800, 2400, 600, 300, 150, and 75. If you look closely at this series, you will see that 1200 baud is missing, since the divider in the 4060 has no Q10 output! If you do not need 1200 baud, this is not a problem.

However, seeing that 1200 baud is used in practice more often than 600 baud, we have put a divide-by-two stage in the circuit after the 4060, in the form of a 74HC74 flip-flop. This yields a similar series of baud rates, in which 600 baud is missing. The trimmer is for the calibration purists; a 33 pF capacitor will usually provide sufficient accuracy. The current consumption of this circuit is very low (around 1 mA), thanks to the use of CMOS components.

The 74HC74 and 74HCT74 are dual positive edge-triggered D-type flip-flops. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip−flop. The Set and Reset inputs are asynchronous.

Features
  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 A
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the JEDEC Standard No. 7A Requirements
  • ESD Performance: HBM 2000 V; Machine Model 200 V
  • Chip Complexity: 128 FETs or 32 Equivalent Gates
  • Pb−Free Packages are Available
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