- Introduction
- Principle of 7 Segment LED Display Decoder Circuit
- Theory Behind the Circuit:
- 7 Segment 7 Segment LED Display Decoder Circuit Design
- K-Map Simplification
- Display Decoder Circuit Operation
- Applications of Display Decoder Circuit
- Limitations of Display Decoder Circuit
Introduction
In digital watches, calculators, clocks, measuring instruments, and digital counters, for example; LED Display Decoder are commonly employed to represent the digits. LCD and LED segments, in general, provide numerical and character display output.
Seven-segment displays, on the other hand, are most typically used to display characters and numbers (in order to make the decimal readout). Typically, these displays are operated by digital IC output stages (for which visual indication of the output stages is required), such as latches and decade counters.
However, these outputs are in the form of 4-bit binary coded decimal (BCD), which is incompatible with driving the seven-segment display directly.
To transform a BCD or binary code into a 7 segment code, a display decoder is used. It has four input lines and seven output lines in most cases. Using logic gates, we create a simple display decoder circuit.
Despite the availability of commercial BCD to 7 segment decoders, creating a display decoder using logic gates may prove to be more cost-effective and knowledge-based.
Principle of Display Decoder Circuit
The basic idea involves driving a common cathode 7-segment LED display using combinational logic circuit. The logic circuit is designed with 4 inputs and 7 outputs, each representing an input to the display IC. Using Karnough’s map, logic circuitry for each input to the display is designed.
Theory Behind the Circuit:
The decoder is the most important aspect of this circuit. A decoder is a type of combinational circuit that converts a binary or BCD (Binary Coded Decimal) number to its decimal equivalent. It could be a BCD to 7 segment decoder or a basic binary to decimal decoder.
Combinational logic circuits is another important element. A system of logic gates with only outputs and inputs is known as a combinational logic circuit. The output of a combinational logic circuit is solely determined by the current state of the inputs. Encoders and Decoders, Multiplexers and De-multiplexers, Adders and Subtractors, and other circuits are good examples.
To comprehend the design and operation of these logic circuits, a thorough understanding of Boolean algebra and logic gates is required. The complementary law, associative law, and De-law, Morgan’s for example, are some essential Boolean algebra rules to follow.
A 7 segment LED display is made up of 8 LEDs arranged in such a way that either all of the anodes or all of the cathodes are common. A common cathode 7 segment display has eight pins: seven input pins designated ‘a’ through ‘g,’ and one common ground pin.
7 Segment Display Decoder Circuit Design
Step 1: The common cathode 7-segment display is analysed in the first step of the design. A 7-segment display is made up of an H-shaped array of LEDs. For each decimal number, a truth table is built using a combination of inputs. The decimal number 1 would, for example, command a combination of b and c. (refer the diagram given below).
Step 2: The second step entails creating a truth table that lists the seven display input signals, as well as the decimal number and four-digit binary values that correlate to them.
The decoder’s truth table is determined by the type of 7-segment display. As previously stated, in order to glow the segment on a common cathode seven-segment display, the output of the decoder or segment driver must be active high.
The truth table of a BCD to seven-segment decoder with common cathode display is shown below. There are 7 different output columns in the truth table, one for each of the 7 segments.
Suppose the column for segment a shows the different combinations for which it is to be illuminated. So ‘a’ is active for the digits 0, 2, 3, 5, 6, 7, 8 and 9.
From the above truth table, the Boolean expressions of each output functions can be written as
a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)
b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)
c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)
d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)
e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)
f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)
g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)
Step 3: The third step involves constructing the Karnough’s map for each output term and then simplifying them to obtain a logic combination of inputs for each output.
K-Map Simplification
The below figures shows the k-map simplification for the common cathode seven-segment decoder in order to design the combinational circuit.
From the above simplification, we get the output values as
Step 4: The final step involves drawing a combinational logic circuit for each output signal. Once the task was accomplished, a combinational logic circuit can be drawn using 4 inputs (A,B,C,D)and a 7- segment display (a,b,c,d,e,f,g) as output.
Display Decoder Circuit Operation
The truth table can be used to understand how the circuit works. When all of the inputs are linked to low logic, the combinational logic circuit’s output will drive all of the output LEDs save “g” to conduct. As a result, the number 0 will appear. The operation would be the same for all other input switch combinations.
BCD to 7 segment decoders are practically available as integrated circuits, such as the 74LS47. A lamping test pin is used for segment testing, a ripple blanking input pin is used to blank out zeros in multiple display systems, a ripple blanking output pin is used for cascade applications, and a blanking input pin is included.
Applications of Display Decoder Circuit
- This circuit can be modified using timers and counters to display the number of clock pulses.
- This circuit can be modified to develop an alphabet display system instead of a decimal number display system.
- It can be used as a timer circuit.
Limitations of Display Decoder Circuit
- This circuit involves lot of logic gates and is quite complex.
- Timing delay by each logic gate is a matter of concern and this circuit might not produce accurate results when used to display count of pulses.
- This is a theoretical circuit and may require few modifications.
