LCD-LED Display

# BCD to 7 Segment LED Display Decoder Circuit

### Outline

• Introduction
• Principle of 7 Segment LED Display Decoder Circuit
• Theory Behind the Circuit:
• 7 Segment 7 Segment LED Display Decoder Circuit Design
• K-Map Simplification
• Display Decoder Circuit Operation
• Applications of Display Decoder Circuit
• Limitations of Display Decoder Circuit

## Introduction

In various digital devices like watches, calculators, clocks, measuring instruments, and digital counters, LED Display Decoders are frequently utilized to represent numerical digits. Generally, both LCD and LED segments are used for displaying numerical and character information.

Seven-segment displays, on the other hand, are predominantly employed for presenting characters and numbers in a way that allows for easy decimal reading. Typically, these displays are controlled by digital IC output components, such as latches and decade counters, which require visual indication of their output states.

However, these outputs are usually in the form of 4-bit binary coded decimal (BCD), which is not directly compatible with driving the seven-segment display.

To convert BCD or binary code into a 7-segment code, a display decoder comes into play. In most cases, it features four input lines and seven output lines. We can construct a simple display decoder circuit using logic gates.

Although there are commercial BCD to 7-segment decoders available, creating a display decoder using logic gates can be a more cost-effective and knowledge-based approach.

## Principle of Display Decoder Circuit

The fundamental concept revolves around controlling a common cathode 7-segment LED display through a combinational logic circuit. This logic circuit is crafted with 4 input signals and 7 output lines, with each one corresponding to an input to the display IC. We employ Karnaugh maps to devise the logic circuitry for each input that interfaces with the display.

## Theory Behind the Circuit:

The centerpiece of this circuit is the decoder, a vital component. A decoder, belonging to the class of combinational circuits, serves the purpose of translating binary or BCD (Binary Coded Decimal) numbers into their corresponding decimal equivalents. It can take the form of either a BCD to 7-segment decoder or a fundamental binary to decimal decoder.

Another critical element involves combinational logic circuits. These are systems of logic gates with inputs and outputs, where the output relies solely on the present input state. Encoders and Decoders, Multiplexers and De-multiplexers, Adders and Subtractors, among others, are examples of such circuits.

To comprehend the design and operation of these logic circuits, a solid grasp of Boolean algebra and logic gates is imperative. Essential Boolean algebra rules include the complementary law, associative law, De Morgan’s law, and others.

A 7-segment LED display comprises 8 LEDs, arranged in a manner where either all the anodes or all the cathodes are common. In the case of a common cathode 7-segment display, it has eight pins: seven input pins denoted as ‘a’ through ‘g,’ and one shared ground pin.

## 7 Segment Display Decoder Circuit Design

Step 1: In the initial stage of the design process, we examine the common cathode 7-segment display. This type of display consists of an H-shaped arrangement of LEDs. To create a truth table, we consider various combinations of inputs corresponding to each decimal number. For instance, the decimal number 1 would activate a combination of b and c segments (please refer to the provided diagram for clarification).

### 7 Segment LED

Step 2: In the second step, we proceed to construct a truth table that outlines the seven input signals for the display along with their corresponding decimal numbers and four-digit binary representations.

The decoder’s truth table is influenced by the specific type of 7-segment display being used. As mentioned earlier, to illuminate a segment on a common cathode seven-segment display, the output from the decoder or segment driver needs to be active in a high state.

The truth table for a BCD to seven-segment decoder designed for a common cathode display is displayed below. It comprises seven distinct output columns, each corresponding to one of the 7 segments.

For instance, let’s consider the column designated for segment ‘a,’ which displays the various combinations for activating it. Segment ‘a’ is active when the digits are 0, 2, 3, 5, 6, 7, 8, and 9.

From the above truth table, the Boolean expressions of each output functions can be written as

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)

f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

Step 3: The third step involves constructing the Karnough’s map for each output term and then simplifying them to obtain a logic combination of inputs for each output.

## K-Map Simplification

The below figures shows the k-map simplification for the common cathode seven-segment decoder in order to design the combinational circuit.

From the above simplification, we get the output values as:

Step 4: The final step involves drawing a combinational logic circuit for each output signal. Once the task was accomplished, a combinational logic circuit can be drawn using 4  inputs (A,B,C,D)and a 7- segment display (a,b,c,d,e,f,g) as output.

## Display Decoder Circuit Operation

The truth table serves as a valuable tool for comprehending the circuit’s operation. When all inputs are set to a low logic state, the output of the combinational logic circuit will drive all of the LEDs except “g” to illuminate. Consequently, the number 0 will be displayed. This principle applies to all other combinations of input switches as well.

Practical BCD to 7-segment decoders can be readily obtained in the form of integrated circuits, like the 74LS47. These ICs often include features such as a lamp test pin for segment testing, a ripple blanking input pin for suppressing zeros in multiple display systems, a ripple blanking output pin for cascade applications, and an input pin for blanking.

## Applications of Display Decoder Circuit

1. This circuit can be modified using timers and counters to display the number of clock pulses.
2. This circuit can be modified to develop an alphabet display system instead of a decimal number display system.
3. It can be used as a timer circuit.

## Limitations of Display Decoder Circuit

1. This circuit involves lot of logic gates and is quite complex.
2. Timing delay by each logic gate is a matter of concern and this circuit might not produce accurate results when used to display count of pulses.
3. This is a theoretical circuit and may require few modifications.

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