Amplifier Circuit Diagrams

Cascode amplifier Schematic Circuit Diagram

A cascode amplifier is a dual-stage circuit comprising a transconductance amplifier followed by a buffer amplifier. The term “cascode” originates from the phrase “cascade to cathode.” This circuit offers numerous advantages compared to a single-stage amplifier, such as enhanced input-output isolation, improved gain, expanded bandwidth, elevated input impedance, increased output impedance, enhanced stability, and higher slew rate. The key factor contributing to the widened bandwidth is the reduction of the Miller effect. Cascode amplifiers are typically constructed using either field-effect transistors (FETs) or bipolar junction transistors (BJTs). One stage is typically configured in the common source/common emitter mode, while the other stage is configured in the common base/common emitter mode.

Miller effect.

The Miller effect is essentially the result of multiplying the stray capacitance between the drain and source of a transistor by the voltage gain. This stray capacitance consistently diminishes the bandwidth, and when combined with the voltage gain, it exacerbates the situation further. The multiplication of stray capacitance results in an augmented effective input capacitance. As we are aware, in amplifier circuits, an increase in input capacitance leads to a reduction in the lower cutoff frequency, resulting in a narrower bandwidth.

To mitigate the Miller effect, one can introduce a current buffer stage at the amplifier’s output or incorporate a voltage buffer stage ahead of the input.

FET Cascode amplifier


The provided schematic illustrates a standard Cascode amplifier employing FETs. The initial stage of this circuit features an FET common source amplifier, with the input voltage (Vin) applied to its gate. The subsequent stage is an FET common gate amplifier, which is driven by the output of the input stage. Rd represents the drain resistance in the output stage, and the output voltage (Vout) is extracted from the drain terminal of Q2.

A notable characteristic of this arrangement is that, due to the grounding of the gate of Q2, the source voltage of FET Q2 and the drain voltage of FET Q1 remain nearly constant. Consequently, the upper FET Q2 offers a low input resistance to the lower FET Q1. This action leads to a reduction in the gain of the lower FET Q1 and subsequently mitigates the Miller effect, resulting in an expanded bandwidth. Importantly, the reduction in the gain of the lower FET Q1 does not impact the overall gain because the upper FET Q2 compensates for this reduction. The Miller effect does not significantly affect the upper FET Q2 since the charging and discharging of the drain-to-source stray capacitance is primarily managed through the drain resistor and the load. The frequency response is affected primarily for high frequencies, well beyond the audio range.

In a Cascode configuration, the output is effectively isolated from the input. FET Q1 maintains almost constant voltage at both its drain and source terminals, while FET Q2 sustains nearly constant voltage at its source and gate terminals. Consequently, there is practically no feedback from the output to the input. The primary focus, in terms of voltage, lies at the input and output terminals, which are efficiently isolated through a central connection maintaining a constant voltage level.

Practical Cascode amplifier circuit


The provided diagram depicts an operational Cascode amplifier circuit utilizing FETs. Within this configuration, resistors R4 and R5 collaborate to create a voltage divider biasing network specifically for FET Q2. R3 serves as the drain resistor for Q2, effectively constraining the drain current. Meanwhile, R2 acts as the source resistor for Q1, accompanied by its by-pass capacitor C1. Additionally, R1 plays a critical role in maintaining a gate voltage of zero for Q1 when there is no input signal present.


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