Clock & Timer Circuit Diagrams

# Clock Pulse Generator Schematic Circuit Diagram

#### Addressing Antique Electric Clock Needs

Over the years, the author has been approached by individuals who have come into possession of ‘antique’ electric clock and require an alternating-polarity pulse driver. Following this, a common inquiry emerges: whether an affordable circuit for this purpose exists. The circuit detailed in this description has proven its effectiveness in three of the author’s clocks for an extended period. The goal was to create a straightforward design that generates a signal on CT=6 (pin 6) of IC2, producing one pulse per minute.

To achieve this, IC3.A is configured as a divide-by-2 circuit, ensuring a consistent signal throughout each 1-minute interval. IC4.E and IC4.F serve as signal buffers, while IC4.D inverts the output of IC4.F. When CT=6 of IC2 goes high, IC3.A receives a clock pulse, causing its Q output to go high. Subsequently, IC4.F and IC4.D charge C3 through R6 (1 MΩ), and the output of IC4.C remains low for approximately a minute. To keep costs down, the author opted to omit automatic adjustment for summer and winter time.

#### Building a 32.768 kHz Oscillator

The core of this setup revolves around IC1, forming a 32.768 kHz oscillator. X1, a crystal akin to those found in affordable digital watches, is utilized and its frequency can be fine-tuned if necessary via trimmer C1.

#### Signal Division and Pulse Generation

The clock signal undergoes division through IC1 and IC2, yielding a signal on CT=6 (pin 6) of IC2 with a frequency of one pulse per minute. IC3.A acts as a divide-by-2 circuit, ensuring a consistent signal within each 1-minute interval. Signal buffering is managed by IC4.E and IC4.F, while IC4.D inverts IC4.F’s output.

#### Pulse Operation and Polarity Alternation

Upon CT=6 of IC2 going high, IC3.A receives a clock pulse, leading to a high Q output. IC4.F and IC4.D subsequently charge C3 via R6 (1 MΩ), keeping IC4.C’s output low for about 1 second. This triggers conduction in T2, T1, and T3. The resulting current through the clock coil illuminates the green LED. After a minute, when CT=6 of IC2 goes high again, IC3.A receives a new clock pulse, causing its Q output to go low. Now, IC4.E charges C4 via R7, making IC4.B’s output low for roughly 1 second, setting IC4.A’s output to logic high. This activates T4, T5, and T6, lighting up the red LED. This alternating pulse mechanism drives the clock with polarity changes.

#### Safety Features and Considerations

Diode D7 safeguards the circuit from reverse polarity supply connections. D8 illuminates constantly when the supply voltage is present. T7 and T8 serve as current limiters in case of a short circuit in the clock mechanism. The peak pulse current can be increased by reducing R16’s value (minimum 2.2 Ω). D11, a dual suppressor diode, clips voltage spikes, although it can be omitted for cost reasons if the clock isn’t heavy-duty or multi-pulse.

#### Important Note on Compatibility

It’s vital to note that this circuit suits pulse-driven clocks operating at 12 V. Modification is necessary for models functioning at 24, 48, or 60 V, although this adaptation isn’t detailed here due to the relative rarity of such models or their potential conversion to 12V operation.

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