voltage converter

D.C.-D.C. Converter Schematic Circuit Diagram

D.C.-D.C. Converter: Enhancing Voltage for Battery Charging

D.C.-D.C. converter: The converter is designed to elevate a direct voltage to nearly double its original level, making it well-suited for amplifying the output of solar cells to meet the charging requirements of lead-acid or NiCd batteries. Capable of delivering a current of up to 3 A, the measurements presented in the table pertain to a load current of 2 A, with the open-circuit output voltage registering approximately 1–1.5 V higher.

Operational Overview with 12V Input and 22V Output

Assuming a 12 V input voltage and a 22 V output voltage, IC1a, R2, and C5 collectively create a rectangular-voltage generator. Simultaneously, the inverted form of this signal is available at the output of IC1d. The interplay of R2C6 introduces a delay to the output of IC1a, ensuring that the output of NAND gate IC1b maintains a duty factor >0.5, with the negative half shorter than the positive half. A similar characteristic is observed in the output of NAND gate IC1c, where the input signal undergoes delay through R5-C7. The output of IC1c undergoes triple inversion and buffering through IC3f, IC3a, and the four paralleled gates IC3b, IC3e before driving the power FET T3.

D.c.-d.c. converter Schematic diagram

Output Drive and Voltage Regulation for IC2a

The output from IC1b serves to drive the small-signal transistor T1. When T1 is in an active state, junction R6-R7 reaches a potential of 2 V without the involvement of diode D1. However, IC2a requires an input signal ranging from 11 to 22 V. This requirement arises because the supply voltage for IC2a, as well as for inverters IC2b–IC2, and the collector voltage of T1 is derived from the doubled output voltage. The negative supply voltage for IC2a is derived from the positive input voltage and diode D1 ensures that the input potential at IC2a stays above 10.5 V.

Alternating Conduction of T2 and T3 for Voltage Doubling

Transistors T2 and T3 operate in alternating conduction. When T2 is on, capacitor C10 charges to the level of the input signal through T3 and D3. Conversely, when T2 is off and T3 is on, C9 undergoes a similar charging process. The charge on capacitor Coo is maintained as D3 prevents its discharge. Due to the series arrangement of the two capacitors, the output voltage becomes twice the input potential.

Ensuring Component Cooling and Wiring Considerations

With multiple inversions and delay networks in place, simultaneous activation of T2 and T3 is prevented. Capacitor C1 buffers the input signal, maintaining a constant load despite the varying current drawn by the circuit. Adequate cooling is crucial for D2, D3, T2, and T3, preferably achieved by mounting these components on a shared heat sink. The bold lines in the circuit diagram indicate heavy-duty wires, emphasizing the importance of keeping them as short as possible, given their 6 A current load. A meticulously crafted converter should achieve an efficiency of 94% at 22.2 V and 1.8 A.

Input and output voltages with a load current of 2 A are:

  • Uin
  • 10  V
  • 12  V
  • 14  V
  • 15  V
  • 16 V
  • Uout
  • 18  V
  • 22  V
  • 26.4  V
  • 28.3  V
  • 30  V

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