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Digital pattern generator

Digital pattern generator: During the construction and testing of digital circuits, there is often a need for an accurately defined bit pattern. The generator described here uses an EPROM to store the bit information for the desired pattern. When switch S1 is pressed, a given pattern is generated once; seven different patterns can be generated simultaneously. The eighth data output of the EPROM is used to mark the end of a pattern.

After S1 has been pressed, gate ICid arranges the resetting of address counter IC2. Gate 1C1c, which is connected to the input of the address counter, functions as a start-stop oscillator that is swit.thed by two NAND gates. These gates are designed to keep the oscillator disabled until the switch is released. Only then are pulses fed to the address counter. The frequency -range of the clock can be varied to individual requirements by altering the value of C3. With values as shown, the frequency can be set with P1 between 15 Hz and 150 Hz.

When a bit pattern is generated, data line D7 must be logic high. At the end of the pattern, this line goes low, whereupon the clock is stopped.

The maximum length of a bit pattern in the circuit as shown is 8191 clock pulses (8×1024-1 stop pulse). If link_ JP1 is set to position B, an external stop pulse can be used.

The circuit draws a current of about 8 mA.
Digital pattern generator Schematic diagram

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