Clock & Timer Circuit DiagramsCounter Circuit DiagramsUPS - Inverter - Power Generator Circuits

Discrete PWM Generator Schematic Circuit Diagram

PWM waveforms are commonly used to control the speed of DC motors. The mark/space ratio of the digital waveform can be defined either by using an adjustable analog voltage level (in the case of a NE555 based PWM generator) or digitally using binary values. Digitally derived PWM waveforms are most often produced by the timer/counter modules in microcontrollers but if you do not want to include a microcontroller in your circuit it’s also quite simple to generate the signals using discrete logic components. An extension of the circuit shown can produce two PWM waveforms from an 8-bit digital input word. Each signal has 15 values. The 8-bit word can be produced for example from an expansion board fitted in a PC or from an 8-bit port of a processor which does not have built-in PWM capability or from a laptop’s printer port.

Discrete PWM Generator Schematic Circuit Diagram

The mark/space ratio is only programmable up to 15/16 rather than 16/16; a binary input of 0000 produces a continuous low on both outputs turning both motors off. Similar circuits often employ a dedicated ‘enable’ input to turn the motors off but it is not necessary for this design. The diagram shows the circuitry required to produce just one waveform. For the full two-channel circuit it is necessary to use an additional 74HC193. The clock signal produced by the HCF4060 generator can be used to drive both channels and the free flip flop in the 74HC74 package can be used for the second channel (the corresponding pin numbers are shown in brackets). Altogether the entire two-channel circuit can be built using just four ICs.

The 74HC74 and 74HCT74 are dual positive edge-triggered D-type flip-flops. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs.
  • Output Drive Capability: 10 LSTTL Loads
  •  Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 A
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the JEDEC Standard No. 7A Requirements
  • ESD Performance: HBM 2000 V; Machine Model 200 V
  • Chip Complexity: 128 FETs or 32 Equivalent Gates
  • Pb−Free Packages are Available

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