The circuit of the frequency doubler may be looked at from different angles. With input signals ≥1 V, T2 and T3 operate as full-wave rectifiers. This means that the fundamental frequency of the input signal is automatically doubled.
With input signals <1 V, the two anti-phase signals produced by T1 from the input signal are applied to the emitters of T2 and T3 and summed. This means that the fundamental frequency will virtually disappear, so that, because of non-linearities, only the harmonics remain: the first harmonic will then become the new fundamental frequency in the out-put signal. This means, of course, that the signal strength reduces appreciably: of an input of 25 mV, only 6 mV remain.
Frequency Doubler Circuit Diagram:
Assuming that the input is sinusoidal, the suppression of the fundamental frequency is optimized with P1. The operating point of T3 should be set with P2 for as near a sinusoidal output as possible in the protype, the out-put signal showed a distortion of 5.5% with an input signal frequency of 1 kHz. The input frequency range is 80 Hz to well over 100 kHz.
Any tendency of T2 or T3 to oscillate may be suppressed by soldering a small ceramic capacitor (about 56 pF) between the base and collector of the transistor. The circuit draws a current of about 4 mA.