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Gated Alarm Schematic Circuit Diagram

Sometimes the need arises for a simple, gated, pulsed alarm. The circuit shown here employs just four components and a piezo sounder and is unlikely to be outdone for simplicity. While it does not offer the most powerful output, it is likely to be adequate for many applications. A dual CMOS timer IC type 7556 is used for the purpose, with each of its two halves being wired as a simple astable oscillator (a standard 556 IC will not work in this circuit, nor will two standard 555’s). Note that the CMOS7556 is supplied by many different manufacturers, each using their own type code prefix and suffix.

Gated Alarm Schematic Circuit Diagram

The relevant Texas Instruments product, for instance, will be marked ‘TLC556CN’. The circuit configuration used here is seldom seen, due probably to the inability of this oscillator to be more than lightly loaded without disturbing the timing. However, it is particularly useful for high impedance logic inputs, since it provides a simple means of obtaining a square wave with 1:1 mark-space ratio, which the ‘orthodox’ configuration does not so easily provide. IC1.A is a slow oscillator which is enabled when reset pin 4 is taken High, and inhibited when it is taken Low. Output pin 5 of IC1.A pulses audio oscillator IC1.B, which is similarly enabled when reset pin 10 is taken High, and inhibited when it is taken Low.

In order to simplify oscillator IC1.B, piezo sounder X1 doubles as both timing capacitor and sounder. This is possible because a passive piezo sounder typically has a capacitance of a few tens of nanofarads, although this may vary greatly. As the capacitor-sounder charges and discharges, so a tone is emitted. The value of resistor R2 needs to be selected so as to find the resonant frequency of the piezo sounder, and with this its maximum volume. The circuit will operate off any supply voltage between 2 V and 18 V. A satisfactory output will be obtained at relatively high supply voltages, but do not exceed 18 V.

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