Since the proposed circuit makes Centronics interface, it is suitable for virtually all types of computer: even older types with a seven-bit Centronics interface, although in their case the possibility of giving an overall reset is not available.
The data from the interface are clocked in IC 18 with the strobe signal. The three least significant bits are applied directly to the three address inputs of eight-bit address-able latches IC9-1C16. These latches are addressed by the next three data bits via address decoder 1C17. In that way, the six least significant bits form the number of the output bit to be addressed (0-63).
Whether the addressed output is high or low depends on data bit 6. Since drivers IC1-1C8 invert, the logic level at the output is inverted with respect to bit 6. The driver ICs can switch up to 500 mA per output. All outputs are reset (the open-collector outputs of the drivers become high-imped-ance) when data bit 7 is high and data bit 6 is low. The state of the three address bits is irrelevant.
When it is required to set one bit and reset the others. rapidly (for instance, by a running light), data bits 6 and 7 can both be made high, whereupon the wanted bit is addressed with the other six bits.
Most loads can be driven directly by the driver ICs, as long as the levels at the output do not exceed 50 V and 500 mA. If it is required to switch the mains, the outputs can be expanded with a solid-state relay.