Output Q1 of this delay circuit becomes active after the switch on period has elapsed and remains, so until the next cycle is begun output Q2, on the other hand, also functions as a monostable; after its mono period has elapsed. Q2 automatically becomes inactive. The mono period can be set between 1 second and 4 seconds with P2. The power-on delay can be set accurately between 1 second and 1 minute with P1 and DIP switch S1.
The circuit is also provided with a count-down indicator: the dight display on LD1 gives continuous information on the remaining switch-on time. The 7-segment display is driven by IC4, a decoder chip that makes only the normal digits (1-9) visible.
When the end of the delay period has been reached, counter IC1 has come to position 0. As a result, the output of IC3a goes high and Ti is switched on. Since at the same time the output of IC3b toggles from high to low, monostable IC2d is start-. The output of the monostable then goes high and switches on T2, indicated by the lighting of the decimal point of the display. Also, start/stop bistable IC2b-IC2c is reset, which disables the counter and the oscillator. To start the next time-out cycle, the bistable must be set afresh, for which, with link JP’ in the position shown in the diagram, the last transition (trailing edge) is required at the input. This is arranged most simply by pressing S2, but the transition may also come from another circuit or from a sensor.
When JP’ is in the other position, the output of the monostable is linked to the input of the start/stop bistable (flip-flop), This results in the time-out cycle being started anew at the end of the mono time. The circuit then operates as an oscillator. The circuit requires a power supply of 8-15 V. It draws a current of about 40 mA, most of which by the display. Transistors T1 and T2 can switch up to 400 mA.