# Low-Drop Diode Schematic Circuit Diagram

#### Addressing High Current Diode Voltage Drops

Many silicon diode exhibit a forward voltage of 1 V or more at high currents. Some types manage to limit the drop to 0.5–0.6 V at currents ranging from 2-3 A, but even this can result in undesirable losses. The circuit detailed here offers a potential solution to mitigate these issues.

#### Utilizing a SIPMOS FET and Sinusoidal Voltage Source

In this circuit, the cathode (C) of T1, a SIPMOS FET, is connected to a sinusoidal-voltage source. The anode (A) acts as a reference point. Capacitor C1 is charged to the peak value of the sinusoidal voltage through D1. This setup ensures a constant power supply for the operational amplifier (op-amp) even during the negative half-periods.

#### Setting the Non-Inverting Input and Opamp Function

The non-inverting input of IC1 is configured to half the peak value of Us through the potential divider R1-P1-R3. Due to the voltage division established by R2-R4, the potential at the inverting input of the operational amplifier (op-amp) will exceed that at the non-inverting input exclusively during the positive half-periods of Us. Consequently, the op-amp activates the drain-source channel of T1 when the voltage at the cathode tends to dip below that at the anode. In this scenario, the current flows through the FET from source to drain, effectively utilizing the internal protection diode in an unconventional manner. This arrangement results in the creation of a FET diode with a forward voltage equal to the product of the current passing through it and the resistance (0.07 Ω).

#### Preset P1 and Precise Adjustment

The calibration of preset P1 governs the anode-cathode potential at which the output voltage of the primarily linearly operating op-amp begins to increase, subsequently triggering the conduction of T1. Precise preset adjustment can only be accomplished with the assistance of an oscilloscope connected to the FET’s drain and source. It should be set to the point where, for the nominal forward current, the voltage across T1 remains minimal during the half-periods when the FET conducts. In the prototype, the measured forward voltage was 0.5 V with an alternating current of 10 A at a frequency of 50 Hz. At 3.3 A, the drop reduced to 0.2 V, and at 300 mA, it minimized to just 0.1 V. It’s noteworthy that the forward voltage remains consistent at currents below the level at which P1 was configured.

#### Considerations for Cathode-Anode Voltage

The circuit’s current draw is only slightly higher than the supply current to IC1. Although the op-amp’s maximum supply voltage is 36 V, it’s essential to maintain the cathode-anode voltage, the’reverse’ voltage of the diode, within a limit of 20 V. This aligns with the BUZ10’s maximum permissible gate-source voltage.

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