Low-drop regulator 2: Nowadays the only reasons for not using a voltage regulator in a power supply are: I have not got one: I need an ‘odd’ voltage: I want to keep the current drain very low.
The regulator shown in the diagram is suitable for currents of 5-10 mA. The two transistors draw only a tiny current. The drop across the regulator depends on the load current and lies between 0.5 V and 1.4 V. The output voltage may be present between 1.8 V and 8 V.
On power-up, there is no voltage at the source of T1, so the FET conducts. Current amplifier T2 then draws base current and is switched on. This arrangement means that the reference (gate) voltage may be taken from a high-resistance potentiometer. The quiescent current depends on the level of the preset output voltage: at 5 V it is a mere 1 mA.
When T2 is switched on, the output voltage will rise to its present level. The base potential of T2, and thus the source potential of Tl, remains about 0.6 V higher than the output voltage so that it rises in step with the output voltage. The gate of T1 is, however, connected to the wiper of 131, whose voltage rises more slowly than the output voltage because the present is a potential divider. Consequently, the gate of T1 becomes and more negative with respect to its source. An equilibrium is soon reached, whereupon the FET reduces the base current of T2 to a degree that ensures the stability of the output voltage.
In normal circumstances, the output voltage vs load current ratio is of the order of 9 mV/mA.