Very Low Power 32-kHz Oscillator Schematic Circuit Diagram

Flexible Frequency Options for Real-Time Clocks

The frequency of a real-time clock is tailored to specific applications. The widely adopted 32768 Hz (32.768 kHz) frequency holds significance because it is a power of 2 (215), enabling precise 1-second periods (1 Hz frequency) through a 15-stage binary counter.

Advantages of the 32-kHz Low-Power Clock Oscillator

The 32-kHz low power clock oscillator presents distinct advantages compared to conventional CMOS inverter-based circuits. Inverter circuits encounter challenges; for instance, supply currents fluctuate significantly across a 3-V to 6-V supply range, making achieving current consumption below 250 μA problematic. Additionally, operations become unreliable due to wide variations in supply voltage, and the inverter’s input characteristics are susceptible to broad tolerances and discrepancies among manufacturers.

Innovative Solution to Previous Challenges

This circuit addresses the aforementioned issues effectively. It operates on a mere 13 μA from a 3 V supply, consisting of a one-transistor amplifier/oscillator (T1) and a low-power comparator/reference device (IC1). T1’s base is biased at 1.25 V through R5/R4 and the reference in IC1. Utilizing any small-signal transistor with a beta of approximately 100 at 5 μA (set by R3), the collector voltage is fixed around 1 V below Vcc. The amplifier’s gain is nominally around 2 V/V. The feedback path around T1 is established by the quartz crystal combined with load capacitors C1 and C3, causing the oscillation due to T1’s 180 degrees of phase shift.

Precision and Efficiency of the Comparator Circuit

Inside the MAX931, the comparator’s bias voltage of 1.25 V is defined by the reference through R2. This ensures the comparator’s input swing is accurately centered around the reference voltage. Operating at 3 V and 32 kHz, IC1 draws a mere 7 μA. While the comparator output can source and sink 40 mA and 5 mA respectively, its moderate rise/fall times of 500 ns and 100 ns can lead to higher switching currents in standard high-speed CMOS logic. To mitigate this, the circuit incorporates an optional 74HC14 Schmitt trigger at the output, balancing the rise/fall times with only a minor increase in supply current.