PARALLEL VOLTAGE REGULATOR SCHEMATIC CIRCUIT DIAGRAMS
A standard parallel voltage regulator circuit is given in figure-1.5. In this circuit; A voltage divider suitable for regulating with the aid of the RP resistor and Q transistor is formed. Output voltage V0 is greater than the peak voltage of the transistor VBE threshold voltage. That is, V0 = VZ + VBE. RP should be selected so as not to exceed the pre-resistance, the maximum current of the transistor, and the maximum allowable power dissipation at the transistor.
For example, if the peak voltage is VZ = 5.6 volts, and the unregulated input voltage is V1 = 16 volts, then the value of Rp is the value of the maximum allowable IC = 1 amp current allowed from the transistor;
If the transistor emitter and collector are short-circuited, then the sum of the input voltage drops above the Rp resistance. Rp is the total power dissipated in the resistor;
The Rp resistor must then be selected so that it can be loaded with a power of 25W. If the current IK is short circuit current;
The output voltage V0 stabilizes the IL current until the voltage at the resistor Rp is greater than the Vi-VZ difference, and likewise unloaded until the IC current is greater than the IC current. Stability then disappears if the current value flowing through the buzzer diode is smaller than the zener break current IZmin. This is also the case when V0 output voltage is Vi- (VZ + VBE). RLmin value when a zener diode with an IZ = 0.02 amperes is used;
It happens. What should be noted here is that the transistor’s base current will be added to the IZmax value. This ana is the real current value of the sinker flow;
It happens. For a low power transistor, for example, 50,
lur and zener power;
obtained. Parallel voltage regulators are rarely used in applications. Because, even in the unloaded state of such voltage regulators, there is a power spending. This is a major disadvantage. In applications, therefore, serial voltage regulators are generally preferred.