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PLL Synthesizer For TV Receivers Schematic Circuit Diagram

Scaling the VCO Signal in Modern TV Tuners:

Contemporary TV tuners typically incorporate mechanisms for downsizing the VCO (voltage-controlled oscillator) signal. The proposed synthesizer employs a Philips Type UV816/6456, featuring a scale factor adjustable to 64 or 256. This tuner operates across the low VHF band, high VHF, and hyperbands, as well as the UHF band. The circuit design centers around a Siemens Type SDA3002 frequency synthesizer IC, controllable by a computer and exclusively functioning with a 64-scaler. Maintaining pin 15 of the tuner ‘open’ ensures this scaler setting. The R2-C2-C1 network forms the filter for the phase-locked loop (PLL), where the charging current’s level is dictated by the value of R1 and bit 14, as outlined in Table 1. In the prototype, stable PLL operation was achieved with both low and high current levels, although the loop exhibited faster response with a high current.

Unique oscillator and PLL setup in the SDA3002:

The SDA3002 features a distinctive oscillator for generating a reference frequency. Internally, the frequency of crystal X1 is scaled down by 4096, resulting in a PLL reference frequency of 976.5625 Hz. The PLL configuration involves entering a data word into the SDA3002, requiring a clock (CPL), an enable signal (PLE), and a data signal (IFO). During each trailing transition (edge) of the clock, a bit is shifted into the IC, conditional on PLE being high, as depicted in Fig. 2. The PLL accepts the entered data into a latch only when PLE transitions to a low state.

PLL synthesizer for TV receivers Schematic diagram

Bit Configuration for Chip Shifting:

To complete the configuration, a total of 18 bits must be shifted into the chip. Of these, 14 bits are dedicated to setting the frequency of the PLL. The 15th bit dictates the charging current, with a high state representing 10 Ir (reference current) and a low state corresponding to Ir. The 16th bit governs the NORM output, while the final two bits determine the state of the band selector outputs on pins 4–7, as detailed in Table 1.

Calculation of the First 14 Bits:

The initial 14 bits are relatively straightforward to calculate once the desired channel frequency (fc), the intermediate frequency (i.ƒ. = 38.9 MHz), the tuner’s scale factor (za = 64), and the PLL’s reference frequency are known. The overall scale factor (z) is determined by the formula z = (fc + i.ƒ.) / (za * ƒr). The result is rounded to the nearest whole number and then split into two parts for IC1, which contains a dual-mode prescaler. The nine most significant bits (MSBs) are obtained by dividing z by 32 and disregarding the digits following the decimal point. The remaining part, z mod 32, constitutes the five least significant bits (LSBs).

As an illustration, for channel 29 with a carrier frequency of 535.250 MHz, the scale factor is calculated as z = (535.25 + 38.9) / (64 * 976.5625) = 9186. Dividing by 32 yields 287 with a remainder of 2, represented in binary as (MSB) 100011111 00010 (LSB). However, the data must be entered in an inverted form, where a logic 1 corresponds to low and a logic 0 to high. Starting with the LSBs, the appropriate levels must be presented at the data input. Diode D1, which is controlled by the lock output via T1, then lights to indicate that the PLL is locked.

Maximum Tuning Voltage and Power Supplies:

The upper limit of the tuning voltage is dictated by the supply voltage, connected to the loop filter through R3. The UV816 tuner necessitates a tuning voltage ranging from 0.7 to 2.8 volts. Notably, the SDA3002 can manage a maximum voltage of 33 volts at its UD output.

Dual Power Requirements:

Two additional power supplies are essential: 12V for the tuner and 5V for IC1 and the prescaler within the tuner. Considering the combined current draw of IC1 and D1 (lighted) is a mere 29 mA, obtaining the 5V rail from the 12V supply via a 5V regulator proves straightforward. Simultaneously, this regulator can supply the required current, approximately 25 mA, for the tuner’s prescaler. Moreover, the 12V supply must cater to the tuner’s current demand, which, in the UV816’s case, is approximately 85 mA. Hence, a total current requirement of approximately 140 mA is necessary.

PLL synthesizer for TV receivers Schematic diagram

PLL synthesizer for TV receivers Schematic diagram

Schematic Circuit Diagram 4

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