Clock & Timer Circuit DiagramsCounter Circuit DiagramsPower Supplies

Power-On Sequencer Schematic Circuit Diagram

This circuit was developed to turn on power supplies in sequence, and then turn them off again in the reverse sequence. This can be helpful for experimenting with equipment and circuits whose power has to be applied and removed in a particular order (like the PC/EPROM-Programmer combination used by Elektor’s Software Service Department; Ed.)

Power-On Sequencer Schematic Circuit DiagramThe heart of the circuit is the venerable 4017 CMOS decade counter. Outputs Q1 to Q4 are used to set latches in the order 1-2-3-4, at which point the count is suspended. Pressing switch S1 allows the counting to continue. Counter outputs Q5 to Q8 are used to reset the latches in the reverse order, i.e., 4-3-2-1. The last output, Q9, is used to halt the counter.

When power is applied, C2 and R2 initially keep the counter reset. When the power supply voltage is stable, the reset signal will go low and the 4017 will begin to count the 1-Hz clock signal supplied by an oscillator consisting of IC1d, R3, and C3. The outputs of the 4017 are actuated in sequence with each rising edge of the clock pulse — but as the next clock pulse comes along the previous output is de-activated.

The latches in the quad RS-latch type 4043 enable the outputs to stay active. IC2 stops counting at Q4 due to IC1b which removes the clock enable signal on pin 13 via IC1a. To enable the 4017 to continue counting and hence turn off the outputs, S1 has to be closed, thus restoring the clock enable on pin 13. Counter outputs Q5 to Q8 are connected to the reset inputs of the latches, so as IC2 increments, the latches are reset in the opposite sequence. The count is finally halted at Q9 by IC1c, which again removes the clock enable signal. Weak pull-up resistors (R4-R7) are used on the latch ‘reset’ inputs to prevent undefined start conditions.

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