Clock & Timer Circuit DiagramsCounter Circuit DiagramsPower Supplies

Power-On Sequencer Schematic Circuit Diagram

Sequential Power Control Circuit

The design of this circuit focuses on the sequential activation of power supplies and their subsequent deactivation in reverse order. This functionality proves invaluable for experimentation with equipment and circuits requiring specific power application and removal sequences. One practical application of this circuit is observed in the PC/EPROM-Programmer combination utilized by Elektor’s Software Service Department.

Power-On Sequencer Schematic Circuit Diagram

Functionality of the 4017 CMOS Decade Counter

Sequential Activation and Resetting

At the core of this circuit lies the reliable 4017 CMOS decade counter. Outputs Q1 to Q4 are utilized to set latches in the sequence 1-2-3-4, temporarily suspending the count. Upon pressing switch S1, the counting process resumes. Counter outputs Q5 to Q8 serve the purpose of resetting the latches in reverse order: 4-3-2-1. The final output, Q9, is instrumental in halting the counter.

Initialization and Counting Process

During the initial power application, C2 and R2 work together to keep the counter in a reset state. Once the power supply voltage stabilizes, the reset signal becomes low, initiating the counting process in the 4017. The counter begins counting the 1-Hz clock signal provided by an oscillator comprising IC1d, R3, and C3. With each rising edge of the clock pulse, the outputs of the 4017 are activated sequentially. However, as the subsequent clock pulse arrives, the previous output deactivates.

Latch Activation and Halt Mechanism

The quad RS-latch type 4043 ensures the outputs remain active. IC2 interrupts the counting at Q4 with the assistance of IC1b, removing the clock enable signal on pin 13 through IC1a. To allow the 4017 to resume counting and deactivate the outputs, S1 needs to be closed, restoring the clock enable on pin 13. Counter outputs Q5 to Q8 are linked to the reset inputs of the latches. As IC2 advances, the latches reset in the reverse sequence. Ultimately, the count comes to a stop at Q9, facilitated by IC1c, which eliminates the clock enable signal. Weak pull-up resistors (R4-R7) are applied to the latch ‘reset’ inputs to prevent undefined start conditions.

Tags

Related Articles

Leave a Reply

Your email address will not be published.

Back to top button
Close
Close