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Radio Control Signal Frame-rate Divider Schematic Circuit Diagram

Model radio-control equipment has evolved considerably over the years, and the humble servo has grown from the 1.5 ms at 50 fps (frames per second) format, to the more precise and powerful digital variety using, typically, 400 fps, and accessories such as helicopter gyros have evolved to make use of these improved servos. As a result, the later generations of gyros often only provide the 400 fps ‘digital’ signal, which is not suitable for use with the older ‘analogue’ servos. All is not lost, as this circuit allows only one frame in eight to reach the servo, replicating the 50 fps system. The prototype version was built using standard ICs, and sits neatly under the gyro (a CSM720 in the test setup) to provide the analogue output. The circuit uses a Type 4017 CMOS decade ring counter, which is clocked by the falling edge of the input via the CP1 (enable) pin, and reset by output 7.

Radio Control Signal Frame-rate Divider Schematic Circuit Diagram 1

Radio Control Signal Frame-rate Divider Schematic Circuit Diagram 2

Radio Control Signal Frame-rate Divider Schematic Circuit Diagram Components list

The first input pulse after reset sets output 1 high, which allows the next input pulse through to the output via a CMOS 4081 OR gate. Thus only one pulse in every eight is fed to the output. The use of negative logic to provide the AND function removes any risk of timing glitches, as the gating signal is established before the input pulse, and is stable for the duration of this pulse.

Other divider ratios can be used by choosing the relevant output for the reset. A miniature PCB with SMD parts on it was designed for the converter to enable it to be incorporated into a model where space is always at a premium! The circuit is best encapsulated in heatshrink sleeving.

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