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RC- 5 infra-red receiver for 80C32 computer

‘RC-5’ is the Philips/Sony standard the received bits are shifted into a 16-hit reg-(JUL” for infra-red (IR) remote control of consistent formed by R4 (low) and R5 (hi0). The audio /video equipment (Ref. 1). The second start bit becomes the MSB. When the circuit and the listing were given enable the 80C32 received word is complete. the two lowest sys-single-board computers (Ref. 2) to receive and ten address bits are moved from R4 to the process IR command signals sent by an RC- LSBs of R5. which leaves the six data bits in 5 compatible IR remote control unit. R4 and the system address bits in the low-The hardware consists of a Siemens SFHSO5A est five bits of R5. IN detector connected directly to the P1.0 port Routine CTRL checks if the check bit has a line of the 80C32 microcontroller. The Sharp changed since the last decoding action. If so, type U60 IR detector may be used as a software decides that a new key has been alternative to the SFHSO5A, with the advance- pressed, or the same key has been pressed stage of higher sensitivity thanks to a pass- again, whereupon the RC-5 system address and that is better ‘tuned’ to RC-5 signals. (that is, the equipment identification number) Note, however, that the SFHSO5A and the and the data (that is. the control action required) IS1U60 have different pin connections. The IR is sent to the PC. If not, the program jumps detector supplies an inverted output signal back to the start. By omitting the JZ LOOP (high level when no IR signal is detected), which instruction. the address and data are trans-has certain ramifications for the software. mated on every received code (‘auto repeat’). The program (see listing) makes use of the EMON51 monitor program (Ref. 3). Since all timings are based on software, it is essential References: that the 80C32 computer runs at a clock speed of 12 MHz. It should also be connected- 1. Universal RC5 code infrared receiver. Elektor ed to a Pc or a terminal. and have the EMON51 Electronics January 1992
system monitor in EPROM. The LOOP routine ensures that the decoding always begins at the start of a new code. COUNT is the count loop proper. If P1.0 goes low during the wait time, R6 is reset, and the waiting starts again. Next, a number of registers are initialized to prepare for the reception of a new code, and the software waits for the first high-to-low transition. Note, however. that a half bit time of the new word has already elapsed when this H-to-L transition is actually detected. This means that 1/a bit time of the second start bit has elapsed after waiting 3/4 bit time. Next, the level at P1.0 Is monitored twice every bit time — first at 1/4, and again at 3/4 of the bit time. The bi-phase modulation used allows the microprocessor to determine if a ‘0’ or a ‘1’ is meant. Actually, it is sufficient if a ‘check’ is carried 0-it only once every bit time. If the synchro-realization is all right, and the check is made at il /4 of the bit time, the correct value is stab-11hed automatically (remember that the input signal is inverted). Checking two times du.r-lig every bit period, however, enables the software In to perceive errors.
2. 8051/80C32 single-boar computer. Elektor Electronics May 1991. 3. 8051/8032 Assembler course (8 installments). Elektor Electronics February to November 1992.

RC- 5 infra



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