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Receiver for RC5 Remote Controls Schematic Circuit Diagram

Software decoding of remote control signals using the RC5 protocol does not present a significant challenge to a modern microcontroller, while for a pure hardware solution specialised RC5 decoder ICs are available. Nevertheless it is interesting to look at how we might process RC5 sig­nals using ordinary components. This way not only do we leam about how the code works, but also the resulting circuit is eas­ier to adapt to different applications.

Although the circuit was originally designed just to display the address and command emitted by a ‘universal remote control’ when each button was pressed, it could be used, for example, to add a remote control facility to an audio amplifier using a stand­ard remote control unit. Indeed, virtuallyany household appliance could be control­led in this way: just choose an address that is not yet allocated and define your own commands.

Receiver for RC5 Remote Controls Schematic Circuit Diagram

The TSOP1736 infrared receiver inverts the bits in the received stream. T1 inverts them again so that they are now available with the correct polarity. The LED connected to its collector indicates when data bits are received.

This signal is low (0 V) for the first half of the start bit and high (5 V) for the second half. This pattern represents a ‘1’ bit, and FF01 (CD4013) will be set. The comple­mentary output of this flip-flop will there­fore be low, enabling the CD4040 divider. The 18 kHz square wave clock for this divider is generated by our old friend the N E555. At the same time, the differentiator formed by C11 and R23 generates a low going pulse which is inverted by Schmitt trigger inverter ST8. The resulting high-going pulse is used to clear the CD4015 shift register.

The Q4 output of the CD4040 (pin 5) carries a square wave at 1125 kHz, cor­responding to a period of 888.8 ps and a pulse width of 444.4 ps. Output Q5 (pin 3) of the CD4040 is inverted by Schmitt trig­ger ST4; the output of this gate is there­fore initially high. The diode matrix forms an AND gate which sets one input to ST1 high just as Q4 rises for the first time. Since the complementary output of FF02 is also high, a high-going pulse (inverted by ST2) is delivered to the CD4015 shift register, causing it to take one sample of the incom­ing data stream. This process is repeated 1.333 ps after the start of each bit period, or exactly three-quarters of the way into each bit. This is the key to the circuit: the value of the signal sampled at this point gives the encoded data bit.

After 14 bits the RC5 packet is complete. At this point a diode matrix forming an AND gate at the outputs of the CD4040 sets FF02. Its output goes low and the clock to the shift register is blocked.

One cycle of the transmit protocol takes 64 bit times. Q11 of the CD4040 counter goes high 32 bit times after the start of the RC5 packet, resetting FF01 and thereby stopping the counter. The data bits at the outputs will be held until a new packet from the ‘trans­mitter sets FF01 again, whereupon the out­put is cleared and the bits read in afresh.

The stop pulse on pin 11 of the CD4040 can be used to validate the output data. When building the circuit it is a good idea to fit a test point at the output of the NE555 so that the 18 kHz clock can be set accurately. All of the timing in the circuit depends on this signal.

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