Receiver for RC5 Remote Controls Schematic Circuit Diagram

Decoding RC5 Signals: A Comparative Approach

Decoding remote control signals utilizing the RC5 protocol poses no significant challenge for modern microcontrollers. Specialized RC5 decoder ICs also provide a hardware solution. However, examining how to process RC5 signals using standard components offers valuable insights. This approach not only enhances our understanding of the code but also yields a circuit adaptable to various applications.

Understanding the Circuit’s Origin and Versatility

Initially designed to display addresses and commands from a ‘universal remote control,’ this circuit’s functionality extends far beyond. It can be utilized to integrate a remote control feature into devices like audio amplifiers using common remote control units. The versatility of this circuit is evident as it can be employed to control numerous household appliances. By selecting an unallocated address and defining unique commands, various devices can be seamlessly controlled.

Inverting and Receiving RC5 Signals

The TSOP1736 infrared receiver reverses the bits in the received stream. T1 inverts them once more, aligning them with the correct polarity. The LED, connected to its collector, signifies the reception of data bits.

Decoding the RC5 Signal: Bit by Bit

The received signal fluctuates between low (0 V) for the initial half of the start bit and high (5 V) for the latter half, indicating a ‘1’ bit. FF01 (CD4013) is set, making the complementary output low, enabling the CD4040 divider. Simultaneously, an 18 kHz square wave clock is generated by the NE555. Additionally, a differentiator (C11 and R23) produces a low-going pulse, inverted by Schmitt trigger inverter ST8. This high-going pulse clears the CD4015 shift register.

Sampling and Decoding: The Core Process

Output Q4 of CD4040 carries a 1125 kHz square wave, representing a period of 888.8 ps and a pulse width of 444.4 ps. Output Q5 (pin 3) is inverted by Schmitt trigger ST4. The diode matrix acts as an AND gate, setting one input high just as Q4 rises for the first time. A high-going pulse is then delivered to the CD4015 shift register, capturing one sample of the incoming data stream. This sample, taken precisely three-quarters into each bit period, determines the encoded data bit.

Completing the Packet and Validating Data

After 14 bits, the RC5 packet concludes. An AND gate, formed by a diode matrix at the CD4040 outputs, sets FF02. FF02 output goes low, blocking the clock to the shift register. A cycle of the transmit protocol spans 64 bit times. Q11 of the CD4040 counter resets FF01 after 32 bit times, halting the counter. The output data remains stable until a new packet arrives, resetting FF01 and allowing fresh data input.

Ensuring Accurate Timing: A Crucial Aspect

The stop pulse on pin 11 of the CD4040 aids in validating the output data. During construction, adding a test point at the NE555 output is advisable, ensuring precise calibration of the 18 kHz clock, as the entire circuit’s timing relies on this signal.