Power Supplies

# Reset from Multiple Power Supplies Schematic Circuit Diagram

#### Voltage Supervisor Chip for Reliable System Reset

Utilizing a voltage supervisor chip is essential to create a stable reset pulse for the processor whenever a ‘brown-out’ condition in the power supply is identified. In configurations with multiple power supplies, especially complex ones, the reliability of the system can be compromised if some supplies are not supervised. The circuit detailed in this setup meticulously monitors all supply rails (specifically +12 V, –12 V, and +5 V) within the system. It triggers a reset pulse to the processor whenever any of these voltages fall outside the acceptable tolerance levels.

#### Comprehensive Supply Rail Monitoring

This circuit offers a comprehensive solution by overseeing all supply rails in the system, including +12 V, –12 V, and +5 V. It utilizes the IC1 (TL7705A) to generate a processor reset when the 5 V rail drops below 4.55 V. The reset pulse width, denoted as td, is determined by the value of the capacitor connected to pin 3, following the formula: td = 12 ⋅ CT ⋅ 10^3. Here, CT is in microfarads (μF), and td is expressed in microseconds (μs).

#### Defining Reset Pulse Width with Capacitor Value

The duration of the reset pulse, crucial for system stability, is calculated based on the value of the capacitor connected to pin 3. This value, denoted as CT in microfarads (μF), directly influences the reset pulse width (td) in microseconds (μs). The precise formula for this calculation is: td = 12 ⋅ CT ⋅ 10^3, ensuring accurate and reliable reset timing for the processor.

#### Determining Reset Pulse Duration

By employing a 100 nF capacitor, a reset pulse lasting approximately 1.2 ms is generated. Pin 6 (RESET) produces an active-high pulse, while Pin 5 (RESET) generates an active-low pulse. Since the outputs are open collector types, external pull-down and pull-up resistors are necessary for proper functioning.

#### External Connections and Level Shifting

The RESIN input (Pin 2) of IC1 receives input from two TL7712A supervisors, monitoring +12 V (IC2) and –12 V (IC3). TL7712A triggers a reset when the supply voltage falls below the 10.8 V threshold level. IC2’s open collector output RES (Pin 5) connects to RESIN on IC1, pulled up to 5 V using a 100 kΩ resistor. IC2’s output can directly link to IC1’s reset input. However, IC3’s output needs a level shifting device before connecting to IC1’s reset input due to its negative voltage level. JFET transistor T1 serves this purpose.

#### JFET Transistor for Level Shifting

The JFET activates when the voltage at its gate-source junction ranges between –2.5 V and –6 V. During IC3’s reset signal issuance, the RES output (Pin 6) drops to ground potential, causing T1 to conduct and initiate a reset for IC1. In other instances, IC3’s RES output is pulled to a negative voltage via the 100 kΩ resistor, ceasing T1’s conduction and releasing the reset. Additionally, a manual reset push button can connect to RESIN of IC1 if necessary.

#### Input Connections and Transient Reduction

The SENSE input (Pin 7) of TL77xx chips links to the positive supply rail. To mitigate the impact of fast transients, a 100 nF capacitor is attached to the reference input (Pin 1). This component helps in stabilizing the circuit against rapid fluctuations.

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