RS-232 Level Shifter with Isolation Schematic Circuit Diagram
This circuit converts between the TTL voltage levels on a UART to the correct levels for an RS-232 interface, with the two sides of the circuit being galvanically isolated from one another. Although ICs are available to do this from manufacturers such as Maxim, they are rather pricey. In principle, the circuit is capable of working at a maximum speed of 4800 baud, but in the lab, we only managed speeds of up to about 2800 baud. The reason behind this is the switching time of the optocoupler, which, according to its datasheet, is 15 µs (Ton) or 30 µs (Toff). Some experimenting with the value of R4 may be worthwhile.
The presence of the optocoupler means that the circuit naturally falls into two isolated, externally powered, halves. The righthand part of the circuit is powered from the DTR and DSR signals on the RS-232 interface (pin 7 and pin 2 of K1). These handshake signals must therefore not be used by the connected device and must be held permanently at +12 V. However since we will be generating negative signaling voltages on this side of the circuit, a simple positive supply is not enough. The trick used here is to tap off the TXD signal on the RS-232 interface via diode D2: in the quiescent state the connected device will be holding this signal at –12 V. Of course, the TXD signal will occasionally go high when the device is transmitting, and so we need C1 to provide a smoothed negative supply.
When something is transmitted to the RS-232 interface, the TXD signal on pin 5 of K1 drives the diode in the optocoupler directly via series resistor R1. However, when pin 5 is at –12 V we must ensure that the reverse voltage across D1 is limited: according to the datasheet, the maximum permitted is 6 V. When a transmission originates on the TTL level side, the receiver transistor in the optocoupler drives a buffer implemented here using four NAND gates. Each gate is wired as an inverter, and it is easy to see from the circuit how overall inversion of the signal is avoided. Three of the gates are wired in parallel to increase the available output drive.
IC1 is powered from a ±12 V supply and so a CMOS device capable of operating at these voltages must be used. Other logic functions besides NAND could be used, as long as the gates can be wired together to make a driver. Individual CMOS gates such as the TC4S81 could also be used, although these are less likely to be found in the average experimenter’s junk box than the 4011 show. The 5×2 header K1 can be connected directly to a 9-way insulation displacement D-sub socket using a flat cable. The wiring is as follows.