Schematic Circuit Diagram 555-Timer as a Bistable Latch proteus simulation

The RS Latch in the 555 Timer can be used with the Reset and Trigger inputs. The output is set or reset with the momentary inputs applied at these inputs. As the S and R inputs are controlled by the outputs of the Op-Amps with trigger and threshold inputs; under the normally open state of the switches the outputs of Op-Amp are such that R, S inputs are 0,0 i.e., LOW state for which, the output of the RS Latch remains in the previous state.

Bistable Latch using 555

Schematic Circuit Diagram 555-Timer as a Bistable Latch proteus simulation

The above circuit is a Bi-Stable latch using Trigger and Threshold inputs of 555 Timer. The output of UC (Upper Comparator) which is Reset input to RS Latch is High when the Threshold input is High or Greater than 2/3 Vcc, so it is Pulled Down. When the Reset input is high with Low Set input to the latch, the output is Reset i.e., Low. The output of LC(Lower Comparator) which is Set input to RS Latch is High when the Trigger input is Low or Lesser than 1/3 Vcc, so it is Pulled High. When the Set input is high with Low Reset input, the output is set, i.e., High.

Bistable Latch using 555

Schematic Circuit Diagram 555-Timer as a Bistable Latch proteus simulation 2

The above circuit is a Bi-Stable latch using Trigger and Reset inputs of 555 Timer. The Threshold input is left open or can be Pulled Down. Irrespective of the Trigger input, When the Reset input is Low, the output is Reset i.e., Low, and so Reset pin is Pulled Up. The output of LC(Lower Comparator) which is the Set input to RS Latch is High when the Trigger input is Low or Lesser than 1/3 Vcc, so it is Pulled Up.

Simulation – Bistable Latch using 555

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