555 timer icProteus Simulation Based Projects

Schematic Circuit Diagram Monostable Latch using 555-Timer proteus simulation

Mono-stable Latch using 555

Schematic Circuit Diagram Monostable Latch using 555-Timer proteus simulation

Using the charging and discharging phases of RC-Circuit as a continuous voltage signal, timing circuits can be designed. When the voltage at trigger input falls from Vcc to below 1/3 Vcc the LC (Lower Comparator) sets and this, in turn, sets the RS-Latch and hence, the output is set. The voltage across the capacitor is connected to the Non-Inverting terminal of the UC (Upper Comparator) and is compared with pre-set 2/3 Vcc at the inverting terminal of the Op-Amp. When the capacitor voltage tends to exceed 2/3 Vcc, the UC sets and this, in turn, resets the RS-Latch and hence, the output is reset.

Simulation – Monostable Latch


Thus, the output is set during the charging time of capacitor from 1/3 Vcc to 2/3 Vcc. This circuit is used to generate time delay circuits like Time delay relay, one-shot operation of the load in sensor based load switching like PIR sensors etc.

Tags

Related Articles

Leave a Reply

Your email address will not be published. Required fields are marked *

Back to top button
Close
Close