Calculator & MeasurementProteus Simulation Based Projects
Schematic Circuit Diagram Op-Amp as a Window voltage detector proteus simulation
To detect the arrival of a particular range of voltage(s) from the swing of an input signal, this circuit is used. Two Op-Amps in comparator mode are used in this circuit. A lower comparator monitors the minimum value of the desired range and upper comparator monitors the maximum value of the desired range. POT Upper and POT Lower are presets for minimum and maximum values.
Op-Amp as Window Voltage Detector
- As in the above image, when the input voltage is less than the Minimum value, then output of Lower Comparator and Upper Comparator are low. The voltages at cathodes of the diode AND Gate are High and Low, so the output is low.
Op-Amp as Window Voltage Detector
- When the input voltage is higher than the maximum preset value, the output of LC is High and UC is High.The voltages at the cathodes of the diode AND Gate are Low and High, so the output is Low.
Window Voltage Detector with Dual Voltage supply
Thus this circuit behaves as a window voltage detector. This circuit can be used with a dual voltage supply and includes negative input voltages also.
An AND gate is an electrical circuit that combines two signals so that the output is on if both signals are present. The output of the AND gate is connected to a base driver which is coupled to the bases of transistors, and alternately switches the transistors at opposite corners of the inverter.
The rule for an AND gate: output is “high” only if the first input and the second input are both “high.” The rule for an OR gate: output is “high” if input A or input B are “high.” The rule for a NAND gate: output is not “high” if both the first input and the second input are “high.”
An AND gate is a digital logic gate with two or more inputs and one output that performs logical conjunction. The output of an AND gate is true only when all of the inputs are true. If one or more of an AND gate’s inputs are false, then the output of the AND gate is false.
