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Simple IR Receiver Schematic Circuit Diagram

Circuit Overview

This circuit has been meticulously crafted to complement the ‘Simple IR Transmitter’ and decode the transmitted signals from it. Its resemblance to the transmitter becomes apparent upon inspection: the received data undergoes decoding via a shift register (74HC4094), which, once again, is regulated by a counter/oscillator (74HC4060). The initiation of the receiver occurs with the first edge detected from the IR-receiver module, effectively triggering monostable IC5a. Utilizing the active-Low output of the module, the circuit employs the negative trigger input. The selected monostable, 74HC4538, is re-triggerable, and a strategic connection from the Q-output to the positive trigger input prevents IC5 from triggering while its output remains active.

Simple IR Receiver Schematic Circuit Diagram 1

Simple IR Receiver Schematic Circuit Diagram 2

Simple IR Receiver Schematic Circuit Diagram 3

Circuit Operation: Enabling IC4

When IC5a is active, its Q output serves to clear the reset input of IC4, thereby enabling it. The oscillator is carefully tuned to 36 kHz, ensuring synchronization between the clock from Q3 of the 4060 and the shift register’s clock, aligning it closely with the transmitter’s clock. To maintain continuous transparency in the internal latch of IC3, its strobe and output-enable pins are tied to logic ‘1’. To prevent active low outputs 5/6/7, the received pulses are inverted by IC2. Outputs 1/2/3/4, instead of being directly connected, are fed to a 4-to-16 demultiplexer. This design ensures that only one output is active at any given time, an essential feature in scenarios like the ‘Switchbox for Loudspeakers’, preventing short circuits or amplifier overloads. The ‘inhibit’ is also linked to IC5a’s output, halting any transient pulses during data clocking, allowing relay contacts to release before another relay engages (break-before-make).

Timing Adjustments and Circuit Current Drain

The pulse width of IC5a is slightly longer than necessary to handle the data (3.9 ms). Depending on the relay specifics, it might be prudent to slightly increase this time (by adjusting R4). The time must exceed the difference between operate and release times. Although release time is typically shorter than the operating time, it’s safer to provide a buffer. IC2b inverts signal Q3 from IC4, ensuring data is clocked halfway through the active bit period. The demultiplexer’s four outputs suit applications like the ‘Switchbox for Loudspeakers’ or the ‘Audio/Video Switch’, both detailed in this issue.

In standby mode, the circuit has a minimal current drain of only 3 mA. The resistors in series with the outputs serve as protection against overloads or short circuits. When driving the ‘Audio/Video Switch’, the output voltage drops to 4.2 V when three boards run in parallel, still adequate to activate relays. For more extensive setups, like six boards for 5.1 surround sound, R5-R8 values should be halved or reduced further


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