SR Flip Flop-Designing using Gates and Applications
- What is a Flip-Flop?
- Overview of Flip Flop
- Flip-Flop using NAND Gates (Technically, RS Flip-Flop)
- Clocked Flip – Flops
- Mechanical Bounce
- How does Flip-Flop Eliminate the Mechanical Bounce?
In this tutorial, we will discuss about one of the basic circuits in Digital Electronics knows as the SR Flip Flop. We will see the basic circuit of an Flip-Flop using NOR and NAND Gates, its working, truth tables, Clocked Flip-Flop and also a simple real-time application.
When the input changes, the output of a Combinational Logic Circuit changes immediately, with the exception of a minor propagation delay.
Another type of circuit is one in which the output is dependent not only on the current input but also on previous inputs and outputs. Sequential Logic Circuits are the name for these types of circuits. What is the best way to acquire the “previous input/output” data? To be able to save the data for later use, we need some type of “memory.” Latches or Flip-Flops are devices or circuits that may store data and operate as a “memory” unit.
NOTE: The phrases “latch” and “flip-flop” will be used interchangeably, despite the fact that they are technically distinct. To put it another way, a flip-flop is a clock-controlled latch, which means the output changes only when a clock signal (a HIGH or L) is present.
What is a Flip-Flop?
A flip-flop is a simple memory device that can store one bit of digital data. It’s a Bistable Electronic Circuit, which means it can only be in one of two stable states: HIGH or LOW. Because a flip-flop is a bistable element, its output remains in one of two stable states until an external event (referred to as a trigger) occurs.
A Flip-Flop can be regarded a Memory Device since it preserves the output long after the input is applied (until something is done to modify it). It can store one binary bit.
Two inverters in series with feedback from the output of the second inverter to the input of the first inverter can be used to make a simple flip-flop. The flip-flop employing inverters is shown in the circuit below.
Let Q1 be the input and Q3 be the output. Initially, assume the feedback is disconnected and Q1 is made 0 (Logic 0, LOW, bit 0) by connecting it to ground. The Q3 will also be 0. Now, if the feedback is connected and the input Q1 is disconnected from ground, the Q3 will still continue to be at 0.
Similarly, instead of ground, if we repeat the same process with 1 (Logic 1, HIGH, bit 1), the output Q3 stays at 1.
This is a simple flip-flop with two stable states and it remains in a particular state, hence a memory, until there is an external event (like change in input in this, case).
Overview of SR Flip Flop
The inverter-based flip-flop shown above is only to demonstrate how it works; it has no practical use because no inputs can be applied. NOR and NAND Gates are used in this situation. A NOR gate can be used to build the inverter-based flip-flop described above.
Ignore the ‘R’ and ‘S’ values for now and let us redraw the above circuit in a more conventional form and rename Q2 as Q and Q3 as Q.
The flip-flop has two inputs, R and S, and two outputs, Q and Q, as shown in the diagram, and the outputs are complementary to one another. Let’s have a look at the various input options and their related outputs.
The fact that Logic ‘1′ is a dominating input for a NOR gate means that if any of its inputs is Logic ‘1′ (HIGH), the output will be Logic ‘0′ (LOW), regardless of the other inputs. Let’s look at the circuit above with this in mind.
Case 1: R = 0 and S = 0
In the first case, the inputs of both the NOR gates are Logic ‘0’. As neither of them are dominating inputs, they have no effect on the output. So, the output retains their previous states i.e., there is no change in the output. This condition is called as Hold Condition or No Change Condition.
R = 0 and S = 1 in Case 2
In this scenario, the ‘S’ input is 1, implying that the NOR Gate B output will be 0. As a result, both NOR Gate A’s inputs become 0 and the NOR Gate A’s output, and hence the value of Q, becomes 1. (HIGH). The S input is known as the SET input because a value of 1 at input S causes the output to flip to one of its stable states and sets it to 1.
R = 1 and S = 0 in Case 3
In this scenario, the ‘R’ input is 1, indicating that the NOR Gate A output will be 0 (i.e., Q will be 0). (LOW). As a result, both of NOR Gate B’s inputs become 0 and the NOR Gate B’s output is 1. (HIGH). When input R is set to ‘1′, the output switches to one of its stable states and is reset to
R = 1 and S = 1 (Case 4)
This input condition is prohibited because it causes both NOR Gates’ outputs to become 0, which violates complementary outputs. Even if this input condition is met, if the next inputs are R = 0 and S = 0 (hold condition), a ‘race situation’ between the NOR Gates occurs, resulting in an unstable or unpredictable output state.
As a result, the input conditions R = 1 and S = 1 are ignored.
So, based on the above-mentioned cases and different combinations of inputs, the truth table for SR Flip is shown in the following table.
|0||0||Last State||No Change|
|1||1||Not Applied (?)||Forbidden|
The logic symbol of an SR Flip-Flop is shown below:
SR Flip-Flop using NAND Gates (Technically, RS Flip-Flop)
An SR flip flop can also be designed by cross coupling of two NAND gates, but the Hold and Forbidden states are reversed. It is an active low input SR flip – flop and hence let us call it RS Flip-Flop. The circuit of SR flip – flop using NAND gates is shown in below figure
An important point about NAND gate is that its dominating input is 0 i.e., if any of its input is Logic ‘0’, the output is Logic ‘1’, irrespective of the other input. The output is 0, only if all the inputs are 1. With this in mind, let us see the working of a NAND based RS Flip-Flop.
Case 1: R = 1 and S = 1
When both the S and R inputs are HIGH, the output remains in previous state i.e., it holds the previous data.
R = 1 and S = 0 in Case 2
The flip flop is in the SET state when R input is HIGH and S input is LOW. The output of NAND gate B, i.e. Q, becomes LOW when R is HIGH. As a result, both of NAND gate A’s inputs become LOW, and the output of NAND gate A, Q, becomes HIGH.
R = 0 and S = 1 in Case 3
The flip flop is in RESET state when R input is LOW and S input is HIGH. When S is HIGH, NAND gate A’s output, Q, becomes LOW. As a result, both of NAND gate B’s inputs become LOW, while the output of NAND gate A, i.e. Q, becomes HIGH.
Case 3: R = 0 and S = 0
When both the R and S inputs are LOW, the flip flop will be in undefined state. Because the low inputs of S and R, violates the rule of flip – flop that the outputs should complement to each other. So, the flip flop is in undefined state (or forbidden state).
The truth table below summarizes the above explained working of SR Flip Flop designed with the help of a NAND gates.
|1||1||Last State||No Change|
|0||0||Not Applied (?)||Forbidden|
The RS Flip-Flop using NAND gates can be converted to have a same truth table as a regular SR Flip-Flip by inverting the inputs. Instead of using inverters, we can use NAND gates with common input as shown in the following figure.
Simple SR flip-flops have the disadvantage of being level sensitive to the control signal (although this is not indicated in the diagram), making them a transparent device. Gated or Clocked SR flip-flops (when the name SR flip-flop is used, it usually refers to clocked SR flip-flops) are introduced to avoid this. The device’s edge sensitivity is due to the clock signal (and hence no transparency).
Clocked SR Flip – Flops
Two types of clocked SR flip – flops are possible: based on NAND and based on NOR. The circuit of clocked SR flip – flop using NAND gates is shown below
his circuit is formed by adding two NAND gates to NAND based SR flip – flop. The inputs are active high as the extra NAND gate inverts the inputs. A clock pulse is given as input to both the extra NAND gates.
Hence the transition of the clock pulse is a key factor in functioning if this device. Assuming it is a positive edge triggered device, the truth table for this flip – flop is shown below.
|↓ or 0 or 1||X||X||Last State||No Change (Hold)|
|↑||0||0||Last State||No Change (Hold)|
|↑||1||1||Not Applied (?)||Forbidden|
The same can be achieved by using NOR gates. The circuit of clocked SR flip – flop using NOR gates is shown below.
The figure suggests a structure of RS flip – flop (as R is associated to the output Q), the functionality of SET and RESET remain the same i.e., when S is high, Q is set to 1 and when R is high, Q is reset to 0.
SR flip – flops are very simple circuits but are not widely used in practical circuits because of their illegal state, where both S and R are high (S = R = 1). But they are used in switching circuits as they provide simple switching function (between Set and Reset).
One such application is a Switch de-bounce circuit. The SR flip-flops are used to eliminate mechanical bounce of switches in digital circuits.
When mechanical switches are pressed or released, they often take a long time to settle down and vibrate multiple times. Switch Bounce or Mechanical Bounce refers to the switch’s non–ideal behaviour. This mechanical bounce will have a tendency to oscillate between low and high voltages, which a digital circuit may interpret.
This can cause pulse signals to vary, and these series of undesired pulses can cause the digital system to malfunction.
For example, in this bouncing period of the signal, the fluctuations in the output voltage are very high and therefore the register counts several inputs instead of single input. To eliminate this kind of behavior of digital circuits, we use Switch Debouncing Circuits and in this case, using SR flip–flops.
How does SR Flip-Flop Eliminate the Mechanical Bounce?
If the set or reset buttons are hit, the output will alter in such a way that it counts more than one signal input, i.e., the circuit may receive some unwanted pulse signals, and so there is no change in outputs at Q due to the mechanical bouncing action of machines.
When the button is pressed, the contact will affect the input of the flip-flop, resulting in a change in the current state and no further circuit/machine consequences for any other mechanical switch bounces. There will be no change if the switch receives any more input, and the SR flip will reset after a short amount of time.
So, the same switch will come to use only after an SR flip – flop executes a state change i.e., only after receiving the single clock pulse signal.
The circuit of a switch de–bouncing circuit is shown below.
The input to the switch is connected to ground (logic 0). There are two pull up resistors connected to each of the input. They ensure that flip – flop inputs S and R are always 1 when the switch is between contacts.
Another circuit can be constructed with NOR SR flip.
A complete beginner’s tutorial on the basic memory circuit known as the SR Latch or the SR -Flop. You learned what is an , its working, its implementation using NOR and NAND Gates, clocked Sr flip and also an important application of SR flip-flop.