Power Supply Sequence Schematic Circuit Diagram
A power supply sequencer and supervisor circuit requires a number of features to make it ideal for power supply management. It must enable seamless cooperation between any number of rails, including timing and sequencing, fast voltage supervision, fault handling, and debugging. Its EEPROM memory should enable complete autonomy, and the I2 C/SMBus interface needs to enable it to be interactive in real time. With flexibility, however, comes some complexity, and there are design choices that need to be made in order to achieve success. This article walks through common scenarios and how to successfully apply the features of the LTC2937 power supply sequencer and supervisor.
Power supply sequence specification
In this example, we introduce the circuit design for the power
supply sequence of 3 systems.
The specifications of the input and output voltages are shown
Figure 1-1 shows the power tree diagram. In this example, the
circuit is configured with 3 power supply ICs. The power supply
ICs are assumed to be switching regulators (DC/DC converters)
or linear regulators (LDO). As a function of the power supply IC,
an enable pin that can control the ON/OFF of the output is
The power shall be turned ON in the order of VOUT1, 2, and 3,
and be turned OFF in the order of VOUT3, 2, and 1. Figure 1-2
shows the schematic diagram.
- Connect SHARE_CLK to VDD through a 3.3k pull-up resistor. The sequencer won’t advance if this open-drain pin doesn’t toggle.
- Connect the open-drain ENn lines through pull-up resistors to a suitable voltage (up to 16.5V). Some DC/DC converters contain their own pull-ups, and may not require an external resistor.
- Connect SCL and SDA to GND, or optionally to VDD through 10k pull-up resistors. We are not using them in this configuration, but they should not be left floating.
- All other pins can take care of themselves – leave them floating. ON, MARGB, WP, ALERTB, FAULTB, RSTB, and SPCLK all have their own built-in weak pull-ups. The ASEL1,2,3 pins will float to set the (7-bit) device I2 C address to 0x44, and WP pulls itself to the write-protected state, but that doesn’t matter because the I2 C bus is unused here.
The control block diagram. DCDC 1, DCDC 2,and DCDC 3 are the power supply ICs of 3 systems. Each output is controlled by the enable (EN) pin. Power Good 1 and 2 monitor the output voltage of the DCDCs when the power is turned ON,and output the “High” signal to the DCDC to be turned ON next when the output voltage reaches the target voltage. Power Good 3 and 4 monitor the output voltage of the DCDCs when the power is turned OFF, and output the “Low” signal to the DCDC to be turned OFF next when the output voltage reaches the target voltage. The Discharge blocks ensure the normal operation of the power supply sequence by rapidly discharging the electric charges stored in the output capacitor of the DCDCs to decrease the voltage when the power is turned OFF. Note that, in this block diagram, the logic is designed as Active High between EN and VOUT of the DCDC blocks, between IN and PGOOD of the Power Good blocks, and between IN and OUT of the Discharge blocks. In addition, the PGOOD pin (output) of the Power Good blocks and the OUT pin of the Discharge blocks are of the open-collector or open-drain type.